• 한국CDE학회논문집
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• 제18권6호
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• pp.417-427
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• 2013

Assembly direction is used in order to confirm the generated assembly sequences in an automatic assembly sequence planning system. Moreover, assembly sequence planners can ascertain the feasibility of a sequence during simulation with assembly direction based in a CAD environment. In other words, assembly direction is essential for sequence optimizing and automatic generation. Based on the importance of assembly direction, this paper proposes a method to select the best direction for the generated assembly sequence using disassembly simulation and geometrical common area between assembled parts. Simultaneously, this idea can be applied to verify the generated assembly sequence. In this paper, the automatic selection of assembly direction and sequence correction system is designed and implemented. The developed algorithms and the implemented system are verified based on case study in the CAD environment.

• 한국시뮬레이션학회논문지
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• 제25권3호
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• pp.133-146
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• 2016

단일 발사대에 탑재된 다수의 유도탄이 다수의 표적과 순차적으로 교전하는 상황에서 발사대는 유도탄이 해당 표적을 타격할 수 있도록 적절한 발사각을 설정하여 구동하게 된다. 이 때, 개별 표적에 대해 할당된 순서대로 교전을 수행하게 되면 전체 교전 시간이 길어지며, 이동하는 표적이 교전 가능 영역을 벗어나게 되어 부분적으로 교전에 실패할 가능성이 있다. 따라서 다양한 표적 배치 상황에서 최적 교전을 수행할 수 있는 발사각 시퀀스(Sequence)에 대한 연구가 필수적이다. 본 연구에서는 다수의 이동하는 표적이 있는 전장 시나리오에서 시뮬레이션을 통해 모든 발사각 시퀀스에 대한 결과를 계산하고, 이 중 전체 교전 시간을 최소화 하는 최적의 발사각 시퀀스를 추출하는 과정을 통해 표적 시나리오에 따른 시퀀스 결정 논리를 모델링하였다. 그리고 그 모델링 결과를 통해 나온 교전 시퀀스와 시뮬레이션을 통해 획득한 최적 혹은 준최적 발사각 시퀀스를 비교함으로써 본 연구에서 제안한 최적 발사각 시퀀스 결정 개념을 검증하였다.

• 한국정보과학회논문지:소프트웨어및응용
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• 제36권6호
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• pp.443-450
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• 2009

시스템 개발 초기 단계에 시스템의 기능적 요구사항이 제대로 반영되었는지를 검사하기 위해 시뮬레이션 기법을 이용한다. 일반적으로 시뮬레이션은 순차도에 나타난 추상적 시나리오를 바탕으로 상태머신을 직접 또는 랜덤으로 수행하는 행태로 진행된다. 시뮬레이션은 분석자가 직접 수행해야 하므로 많은 시간과 노력이 소요된다. 이 논문에서는 순차도 기반의 상태 머신의 시뮬레이션의 자동화 기법을 제공한다. 일반적으로 순차도와 상태머신의 추상화 레벨이 달라서 순차도에서 상세 시뮬레이션 트레이스를 추출하기가 쉽지 않다. 이 연구에서는 상태 머신을 LTS 모델로 변환하여 합성적 분석, 트랜지션 축약 등의 분석 방법을 적용하여 순차도와 동일한 추상화 레벨로 변환한 다음, 시나리오 포함여부를 검사한 후 해당 시나리오의 상세 시뮬레이션 트레이스를 생성한다. 이러한 시뮬레이션 트레이스는 순차도에 기술된 시나리오를 기반으로 시뮬레이션을 자동으로 수행할 뿐만 아니라, 특정 시스템 상태까지 자동 시뮬레이션할 수 있으므로 시뮬레이션을 효율적으로 진행할 수 있다.

• 소성∙가공
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• 제3권3호
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• pp.359-374
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• 1994

Process sequence design in sheet metal forming process by the finite element method is investigated. The forming of sheet metal into a washing machine container is used to demonstrate the design of an improved process sequence which has fewer operations. The design procedure makes extensive use of the finite element method which has simulation capabilities of elastic-plastic modeling. A one-stage process to make an initial blank to the final product is simulated to obtain information on metal flow requirements. Loading simulation for a conventional method is also performed to evaluate the design criteria which are uniform thickness distribution around the finished part and maximum punch load within limit of available press capacity. The newly designed sequence has two forming operations and can achieve net-shape manufacturing, while the conventional process sequence has three forming operations. This specific case conventional process sequence has three forming operations. This specific case can be considered for application of the method and for development of the sequence design methodology in general.

• Journal of Information Processing Systems
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• 제19권3호
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• pp.370-376
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• 2023

Aiming at the problems of low image enhancement accuracy, long enhancement time and poor image quality in the traditional robot sequence motion image enhancement methods, an adaptive enhancement method for robot sequence motion image is proposed. The feature representation of the image was obtained by Karhunen-Loeve (K-L) transformation, and the nonlinear relationship between the robot joint angle and the image feature was established. The trajectory planning was carried out in the robot joint space to generate the robot sequence motion image, and an adaptive homomorphic filter was constructed to process the noise of the robot sequence motion image. According to the noise processing results, the brightness of robot sequence motion image was enhanced by using the multi-scale Retinex algorithm. The simulation results showed that the proposed method had higher accuracy and consumed shorter time for enhancement of robot sequence motion images. The simulation results showed that the image enhancement accuracy of the proposed method could reach 100%. The proposed method has important research significance and economic value in intelligent monitoring, automatic driving, and military fields.

• 소성∙가공
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• 제4권1호
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• pp.28-38
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• 1995

An integrated process planning system can determine desirable operation sequences even if they have little experience in the design of multistage cold forging process. This system is composed of seven major modules such as input module, pre-design module, formability check module, forming sequence design module, forming analysis module, FEM verification module, and output module which are used independently or in all. The forming sequence for the part can be determined by means of primitive geometries such as cylinder, cone, convex, and concave. By utilizing this geometrical characteristics(diameter, height, and radius), the part geometry is expressed by a list of the primitive geometries. Accordingly, the forming sequence design is formulated as the search problem which starts with a billet geometry and finishes with a given product one. Using the developed system, the sequence drawing with all dimensions, which includes the dimensional tolerances and the proper sequence of operations for parts, is generated under the environment of AutoCAD. Several forming sequences generated by the planning system can be checked by the forming analysis module. The acceptable forming sequences can be verified further, using FE simulation.

• 한국군사과학기술학회지
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• 제11권5호
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• pp.23-33
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• 2008

In this paper, we verify the performance of LDPC coded OFDM/DS system by Monte-Carlo simulation of BER on Eb/No. The simulation results show that LDPC coded OFDM/DS has a strong anti-jamming characteristic over pulse-noise jammer and partial-band noise jammer. The performance of LDPC coded OFDM/DS system is evaluated on both faded waveforms and non-faded waveforms. For non-faded waveforms, high coding gain is attained due to LDPC, even when waveforms have short PN sequence and JSR is only 5dB. Especially, the increase in the repeated number of LDPC decoding enhances coding gain. However, faded waveforms cannot achieve sufficient average effect when PN sequence is short. High coding gain of faded waveforms can be achieved by extending length of PN sequence. In addition, we compare LDPC coded OFDM/DS system with Convolutional coded OFDM/DS system. The simulation results illustrate that when LDPC coded OFDM/DS system with short PN sequence has sufficient average effects, the system shows lower BER than Convolutional coded OFDM/DS system with long PN sequence.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 추계학술대회 논문집
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• pp.143-144
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• 2016

The circulating current control within the phase legs is one of the main control objectives in a modular multilevel converter (MMC) under different operating conditions. This paper proposes a control strategy of circulating currents in the MMC under unbalanced voltage by using a proportional-resonant (PR) controller. Under the unbalanced voltage, the circulating currents in the MMC consists of three components such as positive-sequence, negative-sequence, and zero-sequence circulating currents. With the PR controller, all components of the circulating current will be directly controlled in the stationary reference frame without decomposing into positive- and negative-sequence components. Thus, the ripples in the circulating currents and the DC current are suppressed under the unbalanced voltage. The effectiveness of the proposed method is verified by simulation results based on PSCAD/EMTDC simulation program.

• 대한전자공학회논문지
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• 제21권6호
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• pp.105-114
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• 1984

본 논문에서는 direct sequence(DS) 방식을 이용한 spread spectrum system에 사용할 수 있는 빠른 초기 동기 방법을 제안하였다. 수식적인 모델을 세우고 해석을 한 후 computer simulation을 거쳐 제안된 system의 성능을 분석하여 sliding correlator에 비해 우수함을 입증하였다. 입력 신호의 signal-to-noise ratio(SNR)가 -18dB에서 초기 동기 시간이 45ms 소요되었다. 이 방법의 hardsware 구현과 실험 결과도 설명하였다.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.