• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.803-807
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• 2001

This paper presents a new control scheme for a DVR (Dynamic Voltage Restorer) system consisting of series voltage source PWM converters. To control the negative sequence components of the source, it is necessary to detect the negative sequence components. Generally, a filtering process is used which has some undesirable effects. This paper suggests a new method for separating positive and negative sequences components. This control system is designed using differential controllers and digital filters. The positive and negative sequences are extracted and controlled individually. The performance of the presented controller and scheme are confirmed through simulation and actual experiment with a 2.5kVA prototype DVR system.

• 전력전자학회논문지
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• 제19권5호
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• pp.399-406
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• 2014

This study investigates the structure and operation of the ITER VS converter and proposes a sequence control method for six series-connected VS converters to reduce reactive power. The operation and the proposed sequence control method are verified through RTDS simulation. The ITER VS converter must supply voltage/current to the superconducting magnets for plasma current vertical stabilization, and the four-quadrant operation must proceed without a zero-current discontinuous section. The operation mode of the VS converter is separated into a 12- and 6-pulse circulating current and transition modes according to the size of the load current. The output voltage of the unit VS converter is limited because of the rated voltage; however, the superconducting coil must increase the operating output voltage. Thus, the VS converter must be connected in a 6-series to provide the required operating output voltage. The output voltage of the VS converters is controlled continuously; however, reactive power is limited within a minimized value of the grid. In this study, the unit converter is compared with converters connected in a 6-series to determine a suitable sequence control method. The output voltage is the same in all cases, but the maximum reactive power is reduced from 100% to 73%. This sequence control method is verified through RTDS simulation.

• Journal of Power Electronics
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• 제19권2호
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• pp.560-568
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• 2019

This paper studies the inherent relationship between currents and zero-sequence components. Then a precise algorithm is proposed to calculate the injected zero-sequence component to control the DC-Link neutral-point voltage balance, which can result in a more efficient and flexible neutral point voltage balance with a desirable performance. In addition, it is shown that carried-based PWM with the calculated zero-sequence component scheme can be equivalent to space-vector pulse-width modulation (SVPWM). Based on the proposed method, the optimal zero-sequence component of the feasible modulation indices is analyzed. In addition, the unbalanced load limitation of the DC-Link neutral-point voltage balance control is also revealed. Simulation and experimental results are shown to verify the validity and practicality of the proposed algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.338-342
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• 1988

Recently, in sequence control systems, high flexibility and maintenance of control software are required. This is because product life cycles become shorter and control specification must be changed frequently. The authors extend the concept of Safe Petri Net to develop the design and analysis tool for sequence control systems taking the safeness and notation of input/output functions into consideration. Extended Safe Petri Net (S-Net) is proposed as such a new graph model and real time scanning algorithm based on S-Net is developed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• Journal of Power Electronics
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• 제18권4호
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• pp.1245-1254
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• 2018

The stability of a grid-connected system (GCS) has become a critical issue with the increasing utilization of renewable energy sources. Under grid faults, however, a grid-connected inverter cannot work efficiently by using only the traditional droop control. In addition, the unbalance factor of voltage/current at the common coupling point (PCC) may increase significantly. To ensure the stable operation of a GCS under grid faults, the capability to compensate for grid imbalance should be integrated. To solve the aforementioned problem, an improved voltage-type grid-connected control strategy is proposed in this study. A negative sequence conductance compensation loop based on a positive sequence power droop control is added to maintain PCC voltage balance and reduce grid current imbalance, thereby meeting PCC power quality requirements. Moreover, a stable analysis is presented based on the small signal model. Simulation and experimental results verify the aforementioned expectations, and consequently, the effectiveness of the proposed control scheme.

• 조명전기설비학회논문지
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• 제29권8호
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• pp.40-48
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• 2015

In this paper, battery charging and discharging circuit with a single voltage power supply is proposed. The proposed circuit has the separated current path and charging-monitoring sequence control scheme. In the charging sequence, the proposed 2-level comparator combined with control signal of the micro-processor can control the constant charging current to protect the over current of the battery. Furthermore, the proposed circuit uses a periodic main power switch control to detect the discharging characteristics to estimate the approximated battery life-time. In the experiments, the proposed emergency power supply for emergency call system has 89% efficiency with 98% power factor. And the proposed sequence control scheme is well operated in the designed emergency power system.

• 대한전자공학회논문지SD
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• 제40권6호
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• pp.431-441
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• 2003

본 논문은 FPGA를 이용하여 시퀀스 제어용 32비트 마이크로프로세서를 설계하였다. 이를 위해 VHDL을 이용하여 톱-다운 방식으로 마이크로프로세서를 설계하였으며, 고속처리의 문제점을 해결하기 위해 프로그램 메모리부와 데이터 메모리부를 분리하여 설계함으로써 인스트럭션을 페치 하는 도중에 시퀀스 명령을 실행할 수 있는 Harvard 구조로 설계하였다. 또한 마이크로프로세서의 명령어들을 시퀀스제어에 적합하도록 RISC형태의 32 비트 명령어로 고정하여 명령어의 디코딩 시간과 데이터 메모리의 인터페이스 시간을 줄였다. 특히 설계된 마이크로프로세서의 실시간 디버깅 기능을 구현하기 위해 싱글 스텝 런, 일정 프로그램 카운터 브레이크, 데이터 메모리와 일치시 정지 기능 등을 구현함으로써 구현된 프로세서의 디버깅을 쉽게 하였다. 또한, 시퀀스제어에 적합한 펄스명령, 스텝 콘트롤 명령, 마스터 콘트롤 명령 등과 같은 비트 조작 명령과, BIN형과 BCD형 산술명령, 배럴 쉬프트명령 등을 구현하였다. 이와 같은 기능들을 FPGA로 구현하기 위하여 자이링스(Xilinx)사의 V600EHQ240(60만 게이트)과 Foundation 4.2i를 사용하여 로직을 합성하였다. Foundation 합성툴 환경에서 시뮬레이션과 실험에서 성공적으로 수행되었다. 본 논문에서 구현된 시퀀스 제어용 마이크로프로세서의 우수성을 보이기 위해 시퀀스제어용 명령어를 많이 가지고 있는 Hitachi사의 마이크로프로세서인 H8S/2148과 성능을 비교하여 본 논문에서 설계된 시퀀스 제어용 프로세서가 우수함을 확인하였다.

• 인지과학
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• 제6권2호
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• pp.81-95
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• 1995

지능형 코스웨어란 학생의 반응을 진단하여 학생의 상태를 예측하고 이에 근거하여 학습자에게 적합한 학습을 수행하는 코스웨어를 말한다. 본 논문에서는 이러한 코스웨어의 제작을 위한 동적인 교수제어를 지원하는 저작도구를 설계한다.또한 융통성있는 교수를 제어하기위해 교안기술언어를 정의하여 동적인 제어와 정적인 제어가 가능하도록 하고 있다.실질적인 응용으로 C언어의 제어구조를 적용 사례로 하여 코스웨어의 작성과정을 보임으로써 그 타당성을 보인다.

• 산업기술연구
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• 제19권
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• pp.217-226
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• 1999

A single phase to three phase power converter with cost effective and simple structure is proposed. The converter consists of rectifier and inverter. The rectifier is composed of a half wave rectifier, a dc link capacitor, and a current limiting inductor, and the inverter is of only two switches with PWM control. For negative sequence operation the inverter output voltage leads the line input by $60^{\circ}$, and for positive sequence operation the inverter output voltage leads by $60^{\circ}$. We can see that positive sequence operation shows higher output voltage, slight harmonic distortion(2%), and better performances such as high efficiency and high power factor. A mathematical model for system analysis is provided, and specifications for selection and control scheme both for start-up and for steady state are analyzed. comparison and operational limits of positive and negative sequence operation are performed, and simulations and experiments are executed to verify the proposed.