• Journal of Power Electronics
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• v.15 no.1
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• pp.268-277
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• 2015

In this paper, a dual-converter three-phase pulse width modulation (PWM) rectifier based on unbalanced one-cycle control (OCC) strategy is proposed. The proposed rectifier is used to eliminate the second harmonic waves of DC voltage and distortion of line currents under unbalanced input grid voltage conditions. The dual-converter PWM rectifier employs two converters, which are called positive-sequence converter and negative-sequence converter. The unbalanced OCC system compensates feedback currents of positive-sequence converter via grid negative-sequence voltages, as well as compensates feedback currents of negative-sequence converter via grid positive-sequence voltages. The AC currents of positive- and negative-sequence converter are controlled to be symmetrical. Thus, the workload of every switching device of converter is balanced. Only one conventional PI controller is adopted to achieve invariant power control. Then, the parameter tuning is simplified, and the extraction for positive- and negative-sequence currents is not needed anymore. The effectiveness and the viability of the control strategy are demonstrated through detailed experimental verification.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.19-30
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• 2015

A static synchronous compensator (STATCOM) applied to rapidly changing, highly unbalanced loads such as electric arc furnaces (EAFs), requires both positive-sequence and negative-sequence current control, which indicates fast response characteristics and can be controlled independently. Furthermore, a delta-connected STATCOM with cascaded H-bridge configuration accompanying multiple separate DC-sides, should have high performance zero-sequence current control to suppress a phase-to-phase imbalance in DC-side voltages when compensating for unbalanced load. In this paper, actual EAF data is analyzed to reflect on the design of current controllers and a pioneering zero-sequence current controller with a superb transient performance is devised, which generates an imaginary -axis component from the presumed response of forwarded reference. Via simulation and experiments, the performance of the positive, negative, and zero-sequence current control of a cascaded H-bridge STATCOM for EAF is verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.422-428
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• 1988

An iterative learning control system is a control system which makes system outputs follow desired outputs by iterating its trials over a finite time interval. In a discrete time system, we proposed one method in which present control inputs can be obtained by a linear combination of the input sequence and time-shifted error sequence at previous trial. In contrast with a continous time learning control system which needs differential opreration of an error signal, the time shift operation of the error sequence is simpler in a computer control system and its effectiveness is shown by a simulation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.463-467
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• 1992

This paper describes the automatic generation of sequence control programs for DCS(Distributed Control System), PLC(Programable Logic Controller) and so on. Since there is no same manufacturing process, it is difficult to standardize sequence programs. We propose the automatic sequence control program generator which is CAD software using knowledge engineering technique.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.351-357
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• 2003

An easy learning elevator originated is opened to compare the existed teaming equipment, and it had a high studied efficiency that the sequence control circuit can open and close with the wire. The structure of equipment to be controlled from the first floor to the fifth floors is demostrated by the constructive apparatus with the lamps to express the function of the open-close of the door according to the cage moving with a mechanical actuation of the forward reverse breaker and the motor of load, and the mechanical actuation of hand-operation control components of push-button S/W and L/S and relay etc. These components let connect each other in order to control of the elevator function with the auto program and the designed sequence control circuit. Consequently the cage could go and come till 1∼5 steps with an auto program of the elevator and the sequence control circuit. The sequence control circuit is controlled by the step of forward and reverse to follow as that the sensor function of L/S1 ∼ L/S5 let posit with the control switchs of S/W1 ∼ S/W5 of PLC testing panel and switchs of S/W1 ∼ S/W5 installed on the transparent acryl plate of the frame. In here, improved apparatus is the hand-auto operation combined learning equipment to study the principle and technique of the originate sequence control circuit and the auto program of PLC.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.107-112
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• 2010

When we design the control system used Programmable Logic controller(PLC), if we program a Sequential Function Chart(SFC), It is easy to understand the sequential flow of control, to maintenance the controller and to describe a program. SFC language is programmed by a single sequence, a select sequence and a parallel sequence. In a select sequence, when the select step is error, the whole process is stopped. If the error step has no connection the whole process, the loss is down when we debugging the program without stopping the whole process. Therefore, this thesis shows the efficient method of remote control for select sequence and we confirmed its feasibility through actual example.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.55-61
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• 2010

When we design the control system used Programmable Logic Controller(PLC) by Sequential Function Chart(SFC), if we use a SFC, it is easy to know the sequential flow of control, to maintenance the controller and to describe a program. We program a SFC by a unique sequence, an alternative sequence and a parallel sequence. If we program a SFC by a alternative sequence, the memory size of a alternative sequence must be larger than the memory size of a unique sequence. Therefore this thesis show an efficient method to reduce a memory size and we confirmed its feasibility through actual example.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2319-2328
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• 2018

This paper introduces a control method for a transformerless MMC-HVDC system. The proposed method can effectively control the grid currents of the MMC-HVDC system under unbalanced grid conditions such as a single line-to-ground fault. The proposed method controls the currents of the positive sequence component and the negative sequence component without separating algorithms. Therefore, complicated calculations for extracting the positive sequence and the negative sequence component are not required. In addition, a control method to regulate a zero sequence component current under unbalanced grid conditions in the transformerless MMC-HVDC system is also proposed. The validity of the proposed method is verified through PSCAD/EMTDC simulation.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.