• Journal of Navigation and Port Research
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• v.29 no.1 s.97
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• pp.91-96
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• 2005

The National Marine Electronics Association(NMEA) is nonprofit-making cooperation composed with manufacturers, distributors, wholesalers and educational institutions. We use the basic port of equipment in order to process the signal from NMEA signal using equipment. When we don't have enough one, we use the multi-port for processing. However, we need to have module development simulation which could multiplex and provide NMEA related signal that we could solve the problems in multi-port application and exclusive equipment generation for a number of signal. For now, we don't have any case or product using NMEA multiplexer so that we import expensive foreign equipment or embody NMEA signal transmission program like software, using multi-port. These have problems since we have to pay lots ci money and build separate processing part for every application programs. Besides, every equipment generating NMEA signal are from different manufactures and have different platform so that it could cause double waste and loss of recourse. For making up for it, I suggest the NMEA multiplexer embodiment, which could independently move by reliable process and high performance single hardware module, improve the memory efficiency of module by designing the optimized Queue, and keep having reliability for realtime communication among the equipment such as main input sensor equipment Gyrocompass, Echo-sound, and GPS.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.670-675
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• 1994

Yhis paper describes a fault diagnosis simulation of the Real-Time Multiple Fault Dignosis System (RTMFDS) for forcasting faults in a system and deciding current machine state from signal information. Comparing with other diagnosis system for single fault,the system developed deals with multiple fault diagnosis,comprising two main parts. One is a remotesignal generating and transimission terminal and the other is a host system for fault diagnosis. Signal generator generate the random fault signal and the image information, and send this information to host. Host consists of various modules and agents such as Signal Processing Module(SPM) for sinal preprocessing, Performence Monotoring Module(PMM) for subsystem performance monitoring, Trigger Module(TM) for multi-triggering subsystem fault diagnosis, Subsystem Fault Diagnosis Agent(SFDA) for receiving trigger signal, formulating subsystem fault D\ulcornerB and initiating diagnosis, Fault Diagnosis Module(FDM) for simulating component fault with Hierarchical Artificial Neural Network (HANN), numerical models and Hofield network,Result Agent(RA) for receiving simulation result and sending to Treatment solver and Graphic Agent(GA). Each agent represents a separate process in UNIX operating system, information exchange and cooperation between agents was doen by IPC(Inter Process Communication : message queue, semaphore, signal, pipe). Numerical models are used to deseribe structure, function and behavior of total system, subsystems and their components. Hierarchical data structure for diagnosing the fault system is implemented by HANN. Signal generation and transmittion was performed on PC. As a host, SUN workstation with X-Windows(Motif)is used for graphic representation.

• Journal of the Korean Society of Industry Convergence
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• v.7 no.2
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• pp.199-205
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• 2004

This paper describes the fault diagnosis method to order to construct CIM in complex system with hierarchical structure similar to human body structure. Complex system is divided into unit, item and component. For diagnosing this hierarchical complex system, it is necessary to implement a special neural network. Fault diagnosis system can forecast faults in a system and decide from the signal information of current machine state. Comparing with other diagnosis system for a single fault, the developed system deals with multiple fault diagnosis, comprising hierarchical neural network (HNN). HNN consists of four level neural network, i.e. first is fault symptom classification and second fault diagnosis for item, third is symptom classification and forth fault diagnosis for component. UNIX IPC is used for implementing HNN with multitasking and message transfer between processes in SUN workstation with X-Windows (Motif). We tested HNN at four units, seven items per unit, seven components per item in a complex system. Each one neural network represents a separate process in UNIX operating system, information exchanging and cooperating between each neural network was done by message queue.

• Journal of Korean Society of Transportation
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• v.10 no.3
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• pp.7-20
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• 1992

The common cycle time for the linded signals is usually determined for the critical intersecion, just because the cpacity of a signalized intersection depends on the cycle time. This may not be optimal since the interactions between the flow and the spatial structure of the route or the area are disregarded in this case. It is common to separate the total delay incurred at signals into two parts, a deterministic or uniform delay and a stochastic or random delay. The deterministic delays and the stochastic delays on the artery particularly related to signal cycle time. For this purpose a microscopic simulation technique is used to evaluate deterministic delays, and a macroscopic simulation technique based on the principles of Markov chains is used to evaluate stochastic delays with over flow queue. As a result of investigating the relations between deterministic delays and cycle time in the various circumstances of spacing of signals and traffic volume. As for stochastic delays the resalts of comparisons of the macroscopic simulation and Newell's approximation with the microscopic simulation indicate that the former is valid for the degree of saturation less than 0.95 and the latter is for that above 0.95. Newell's argument that the total stochastic delay on an arterial is dominated by that at or caused by critical intersection is certified by the simulation experiments. The comprehensive analyses of the values of optimal cycle time with various conditions lead to a model. The cycle time determined by this model shows to be approximately 70% of that calculated by Webster's.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.11
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• pp.135-146
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• 1997

This paper describes fault diagnosis method in complex system with hierachical structure similar to human body structure. Complex system is divided into unit, item and component. For diagnosing this hierarchical complex system, it is necessary to implement special neural network. Fault diagnosis system can forecast faults in a system and decide from current machine state signal information. Comparing with other diagnosis system for single fault, the developed system deals with multiple fault diagnosis comprising Hierarchical Neural Network(HNN). HNN consists of four level neural network, first level for item fault symptom classification, second level for item fault diagnosis, third level for component symptom classification, forth level for component fault diagnosis. UNIX IPC(Inter Process Communication) is used for implementing HNN wiht multitasking and message transfer between processes in SUN workstation with X-Windows(Motif). We tested HNN at four units, seven items per unit, seven components per item in a complex system. Each one neural newtork operate as a separate process in HNN. The message queue take charge of information exdhange and cooperation between each neural network.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.6
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• pp.11-17
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• 2001

Design and implementation of the MAC protocol processor prototype for high speed wireless LAN, which has interface with 5GHz OFDM PHY layer, is presented. We analyze the IEEE 802.11 MAC protocol specification and then separate the MAC protocol functions to be implemented by hardware and firmware and define the interface in which frames can be exchanged. That is, it is considered that high speed queue processing and interfaces with RISC processor and OFDM PHY layer. Protocol control and transmission/reception functions of the MAC functions are implemented in hardware in order to guarantee high speed processing in MAC layer. The developed MAC hardware block operates at 10MHz main clock. Therefore, transmission rate in PHY layer is about 80Mbps because data transmission/reception between MAC layer and PHY layer is performed as unit of octet. The designed FPGA MAC function chip has been implemented in wireless LAN test board and it is verified that DCF function is operated correctly.

• The Journal of the Korea Contents Association
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• v.16 no.2
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• pp.163-173
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• 2016

Recently, massive amounts of stream data have been studied for distributed processing. In this paper, we propose an incremental stream data processing method based on in-memory in big data environments. The proposed method stores input data in a temporary queue and compare them with data in a master node. If the data is in the master node, the proposed method reuses the previous processing results located in the node chosen by the master node. If there are no previous results of data in the node, the proposed method processes the data and stores the result in a separate node. We also propose a job scheduling technique considering the load and performance of a node. In order to show the superiority of the proposed method, we compare it with the existing method in terms of query processing time. Our experimental results show that our method outperforms the existing method in terms of query processing time.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11S
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• pp.3684-3693
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• 2000

In this paper, performance of a nonblocking high speed packet switch with switching capacity m which adopts a dynamic priority control function (DPCF) of a threshold- based Bernoulli priority jump (TBPJ) scheme is considered. Each input queue has two separate buffers with different sizes for two classes of traffics, delay-sensitive and loss-sensitive traffics, and adopts a TBPJ scheme that is a general state-dependent Bernoulli scheduling scheme. Under the TBP] scheme, a head packet of the delay-sensitive traffic buffer goes into the loss -sensitive traffic buffer with Hernoulli probability p according to systems states that represent the buffer thresholds and the number of packets waiting for scheduling. Performance analysis shows that TBPJ scheme obtains large performance build-up for the delay-sensitive traffic without performance degradation for the loss-sensitive traffic. In addition to, TBP] scheme shows better performance than that of HOL scheme.