• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.61.2-61.2
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• 2007

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.172-173
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• 2002

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.100-105
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• 2004

The influencing factors on the OPC (optical proximity correction) results are quantitatively analyzed using OPCed L/S patterns. ${\sigma}$ values of proximity variations are measured to be 9.3 nm and 15.2 nm for PR-A and PR-B, respectively. The effect of post exposure bake condition is assessed. 16.2 nm and 13.8 nm of variations are observed. Proximity variations of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate the OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4, 13.9, and 15.2 nm are observed for the mask mean-to-targets of 0, 2 and 4 nm, respectively. The decrease the OPC grid size from 1 nm to 0.5 nm enhances the correction resolution and the OCV is reduced from 14.6 nm to 11.4 nm. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The critical dimension (CD) uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 9.9 nm and 8.7 nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved. The decrease of OPC grid size is shown to improve not only the proximity correction, but also the uniformity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.120-126
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• 2005

We have proposed a characteristic method to estimate real composition when multi component oxide films are deposited by ALD. Final atomic concentration ratio was theoretically calculated from the film densities and growth rates for $HfO_2$ and $Al_2O_3$ using ALD processed HfxAhOz mms.W e have transformed initial source feeding ratio during deposition to fins] atomic ratio in $Hf_xAl_yO_z$ films through thickness factors ($R_{HFO_2}$ ami $R_{Al_2O_3}$) ami concentration factor(C) defined in our experiments. Initial source feeding ratio could be transformed into the thickness ratio by each thickness factor. Final atomic ratio was calculated from thickness ratio by concentration factor. It has been successfully confirmed that the predicted atomic ratio was in good agreement with the actual measured value by ICP-MS analysis.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.21-24
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• 2003

Seam seal welding on the semiconductor package is a process for sealing the packages of semi-conductors, crystal parts, saw filters and oscillators with lid plate by seam welding. This paper presents the development process of automatic seam seal welding system. In this process, the process algorithm, high precision welding current control, design of welding head, high speed and high precision feeding mechanism and user interface process control program technologies are included.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.136-139
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• 2004

The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.

• Korean Journal of Computational Design and Engineering
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• v.19 no.4
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• pp.402-409
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• 2014

Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.3
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• pp.154-163
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• 2010

Process monitoring of output variables affecting final performance have been mainly executed in semiconductor manufacturing process. However, even earlier detection of causes of output variation cannot completely prevent yield loss because a number of wafers after detecting them must be re-processed or cast away. Semiconductor manufacturers have put more attention toward monitoring process inputs to prevent yield loss by early detecting change-point of the process. In the paper, we propose the method to efficiently monitor functional input variables in multi-phase semiconductor manufacturing process. Measured input variables in the multi-phase process tend to be of functional structured form. After data pre-processing for these functional input data, change-point analysis is practiced to the pre-processed data set. If process variation occurs, key variables affecting process variation are selected using contribution plot for monitoring efficiency. To evaluate the propriety of proposed monitoring method, we used real data set in semiconductor manufacturing process. The experiment shows that the proposed method has better performance than previous output monitoring method in terms of fault detection and process monitoring.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1323-1324
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• 2008

We developed the Hyper-thermal Neutral Beam (HNB) sputtering process as a plasma damage free process for ITO top anode deposition on inverted Top emission OLED (ITOLED). For examining the effect of the HNB sputtering system, Inverted Bottom emission OLEDs (IBOLED) with ITO top anode electrode were fabricated; the characteristics of IBOLED using HNB sputtering process shows significant suppression of plasma induced damage.