• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2218-2219
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• 2008

본 연구는 반도체 기판 히팅 장치의 새로운 구조에 관한 것으로 기판의 바닥면에 밀착된 가열 플레이트층의 직접가열 구조에 따른 빠른 열 응답성 및 열손실 최소화를 이룰 수 있다. 또한 가열 플레이트층에 내장된 히팅 수단인 시즈히터의 접촉면적을 늘려 가열 유효면적 증가와 같은 효과를 갖는다. 이를 위해 감광막이 코팅된 기판과, 상기 기판의 바닥면에 밀착되는 가열 플레이트층, 절연 및 열손실을 최소화하기 위해 상기 가열 플레이트층의 바닥면에 밀착되는 운모층, 상기 운모층의 하부에 밀착되어 바닥 플레이트층으로 이루어지되, 상기 가열 플레이트 층은 바닥면 전체에 걸쳐 연속되는 홈부를 형성하고, 상기 홈부로는 기판을 가열하기 위한 시즈히터가 삽입되어 구성된다. 새로운 기판 히팅 구조를 사용하여 시간 경과에 따른 가열 플레이트의 온도 변화를 확인 한 결과, 간접가열방식인 기존 방식에 비해 약 40 %의 전력 절감효과가 있는 것으로 확인 되었다.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.86-88
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• 2007

In the semiconductor manufacturing industry, the heterodyne laser interferometer plays as an ultra-precise measurement system. However, the heterodyne laser interferometer has some unwanted nonlinearity error which is caused from frequency-mixing. This is an obstacle to improve the measurement accuracy in nanometer scale. In this paper we propose a compensation algorithm based on RLS(recursive least square) method and artificial intelligence method, which reduce the nonlinearity error in the heterodyne laser interferometer. With the capacitance displacement sensor we get a reference signal which can be transformed into the intensity domain. Using the back-propagation Neural Network method, we train the network to track the reference signal. Through some experiments, we demonstrate the effectiveness of the proposed algorithm in measurement accuracy.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.502-506
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• 1999

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, so it is important to control the chipping generation in the process of dicing. This paper deals with chipping of the silicon wafer dicing. The relationships between the dicing force and the wafer chipping are investigated. It is confirmed that the wafer chipping increases as the dicing force increases.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.3
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• pp.28-32
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• 2002

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, therefore it is important to investigate the machining quality of $\mu$ BGA. This paper deals with machining characteristics of the $\mu$ BGA singulation. The relationships between the singulation face and machining quality of the $\mu$ BGA singulation are investigated. It is confirmed that machining quality improves as the singulation force decreases.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.3
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• pp.111-119
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• 2006

The ultra-precision stage is demanded for some industrial fields such as semiconductor lithography, ultra-precision machining, and fabrication of nano structure. A new stage was developed for those applications in order to obtain nano meter resolution. This stage consists of symmetric double parallelogram mechanism using flexure hinges. The mechanical properties such as strength of the flexures and deformations along the applied force were analyzed using FEM. The stage is actuated by a piezoelectric actuator and its movement was measured by a ultra-precision linear encoder. In order to improve positioning performance, a PID controller was designed based on the identified second order transfer function. Experimental results showed that this stage could be positioned within below 5 nm resolution irrespective of hysteresis and creep by the controller.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.18 no.2
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• pp.228-233
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• 2009

An ultra-precision stage is used in many industrial areas such as precision machine tools or semiconductor apparatus. These stages used to be driven by piezoelectric actuators in order to obtain ultra precision positioning resolution. Piezoelectric actuator can be moved fast in nanometer resolution. However, it has relatively large non-linear characteristics like hysteresis and creep curve. Although several kinds of control techniques have been developed, controller design method is still complicated. In this paper fuzzy control rules are developed intuitively. In order to verify the performance a series of experiments were conducted and the results were compared with those of the PID controller case.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.22 no.11
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• pp.1564-1570
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• 1998

In-situ particle monitors(ISPMs) are widely used for monitoring contaminant particles in vacuum-based semiconductor manufacturing equipment. In the present research, the performance of a Particle Measuring Systems(PMS) Vaculaz-2 ISPM at subatmospheric pressures has been studied. We created uniform upstream conditions of particle concentration and measured the detection efficiency, the lower detection limit, and the size response of the ISPM using uniform sized methylene blue aerosol particles. The effect of particle size, particle velocity, particle concentration, and system pressure on the detection efficiency was examined. Results show that the detection efficiency of the ISPM decreases with decreasing chamber pressure, and with increasing mass flow rate. The lower detection limit of the ISPM, determined at 50 % of the measured maximum detection efficiency, was found to be about $0.15{\sim}0.2{\mu}m$, which is similar to the minimum detectable size of $0.17{\mu}$ given by the manufacturer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.378-381
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• 2003

The chemical mechanical polishing (CMP) has been widely accepted for the global planarization of multi-layer structures in semiconductor manufacturing However, cost of ownership (COO) and cost of consumables (COC) were relatively increased because of expensive slurry. In this paper, the effects of different slurry composition on the oxide CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity. We prepared the various kinds of slurry. In order to save the costs of slurry, the original slurry was diluted by de-ionized water (DIW). And then, alunima abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.1
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• pp.14-17
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• 2005

In this paper, an automated methodology for generating model parameters considering real manufacturing processes is presented with verified results. In addition, the outcomes of applications to the next generation of flash memory devices using the parameters calibrated from the process specification decision are analyzed. The test vehicle is replaced with a well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for a flash memory device. The calibration errors are less than 5% of a full chip operation, which is acceptable to designers. The results of the calibration are then used to predict the I-V curves and the model parameters of various transistors for the design of flash devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.6
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.