• 제목/요약/키워드: Semiconductor manufacturing

검색결과 932건 처리시간 0.031초

EPD 신호검출에 의한 플라즈마식각공정의 이상검출 (Malfunction detection in plasma etching process using EPD signal trace)

  • 이종민;차상엽;최순혁;우광방
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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    • pp.1360-1363
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    • 1996
  • EPD(End Point Detection) is used to decide etching degree of layer which must be removed at wafer etching process in plasma etching process which is one of the most important process in semiconductor manufacturing. In this thesis, the method which detects malfunction of etching process in real-time will be discussed. Several EPD signal traces are collected in normal plasma etching condition and used as reference EPD signal traces. Critical points can be detected by applying differentiation and zero-crossing techniques to reference EPD signal. Mean and standard deviation of critical parameters which is memorized from reference EPD signal are calculated and these determine the lower and higher limit of control chart. And by applying statical control chart to EPD signals which are collected in real etching process malfunctions of process are detected in real-time. By means of applying this method to the real etching process we prove our method can accurately detect the malfunction of etching process and can compensate disadvantage of current industrial method.

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Four Point Bending Test for Adhesion Testing of Packaging Strictures: A Review

  • Mahan, Kenny;Han, Bongtae
    • 마이크로전자및패키징학회지
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    • 제21권4호
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    • pp.33-39
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    • 2014
  • To establish the reliability of a packaging structures, adhesion testing of key interfaces is a critical task. Due to the material mismatch, the interface may be prone to delamination failure due to conditions during the manufacturing of the product or just from the day-to-day use. To assess the reliability of the interface adhesion strength testing can be performed during the design phase of the product. One test method of interest is the four-point bending (4PB) adhesion strength test method. This test method has been implemented in a variety of situations to evaluate the adhesion strength of interfaces in bimaterial structures to the interfaces within thin film multilayer stacks. This article presents a review of the 4PB adhesion strength testing method and key implementations of the technique in regards to semiconductor packaging.

초정밀위치결정을 위한 델타스테이지의 최적 설계 및 컴퓨터 시뮬레이션에 관한 연구 (A Study on the Optimal Structural Design and Computer Simulation of Delta Stage for ultra Precision Positioning)

  • 김재열;김영석;송찬일;곽이구;한재호
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2001년도 춘계학술대회 논문집
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    • pp.221-225
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    • 2001
  • Recently, high accuracy and high precision are required in various industrial fields that are composed of semiconductor manufacturing apparatus and ultra precision positioning apparatus and information system and so on. The positioning technology is a very important one among them. This technology has been rapidly developed, its field needs for positioning accuracy to high as submicron. It is expected that accuracy with 10 nm in precision working and accuracy with 1 nm in ultra precision working are reached at the beginning of 2000s. Recently, to accomplish this positioning technology, many researches are concerned about it and make efforts it. This paper contain design technology of ultra precision 2-axis(X-Y Delta) stage for materialize to positioning accuracy with submicron, where, Delta stage is design as optimum against load and disturbance. And computer simulation is performed for stability and dynamic characteristic of Delta stage.

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Distortion of Eelectrical Double Layer in Liquid Filtration by Fibrous Filters

  • Lee, Myong-Hwa;Hirose, Shogo;Otani, Yoshio
    • 한국입자에어로졸학회지
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    • 제10권3호
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    • pp.99-108
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    • 2014
  • Liquid filtration by membrane filters is essential for the preparation of ultrapure water in semiconductor manufacturing processes. The separation of submicrometer particles suspended in ultrapure water with a laminated fibrous membrane filter was studied numerically and experimentally in the present work. We found that an electrical double layer around a single fiber expanded to a large extent at a low ion concentration, as in ultrapure water, and deformed toward the upstream of the fiber with increasing filtration velocity. Since an increase in the electrical double-layer thickness leads to a decrease in the electrical potential gradient, particles with the same polarity as the fiber approach the fiber more easily and are captured at a high filtration velocity. Experimental results also confirmed that the collection efficiency of polystyrene latex(PSL) particles through a PTFE filter became higher as the filtration velocity increased.

전력 전자회로의 디지탈 시뮬레이션에 관한 연구 (A Study on the Digital Simulation of Power Electronic Circuits)

  • 황선진;정태경;윤병도
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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    • pp.231-234
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    • 1989
  • In recent, due to the advanced development of the power semiconductor devices, the Digital Simulation becomes essential in order to investigate the behavior of the system before the manufacturing of the system by using computer for design and analysis of Power Electronic systems. This paper develope the program so-called PECA, which can be applied for the Power Electronic circuits composing of power transistors, thyristers, GTOs and power FET, etc. We consider transistor DC chopper circuit and prove the effectiveness of our program by both the experiment and simulation.

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Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC

  • Song, Jaehoon;Jung, Jihun;Kim, Dooyoung;Park, Sungju
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권3호
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    • pp.345-355
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    • 2014
  • Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

레이저 마커용 빔 정렬장치의 공리적 설계 (Axiomatic Design of a Beam Adjuster for Laser Marker)

  • 신광섭;이정욱;박경진
    • 대한기계학회논문집A
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    • 제26권9호
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    • pp.1727-1735
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    • 2002
  • The usage of beam scanning type laser marker is rapidly increasing in the field of semiconductor equipment. A device called ″beam adjuster″ is employed to adjust the visible diode laser, which points the marking position for various setting. The device is very sensitive to manufacturing tolerance and assembly condition. Axiomatic approach has been applied to the design of the device. An existing design is analyzed based on the Independence Axiom. The existing design is found to violate the axiom. Two new designs are proposed to satisfy the Independence Axiom. The Information Axiom is utilized to evaluate the designs. A design is selected to have the minimum information content. The significance of this research is that a full cycle of axiomatic design is applied to a real engineering product.

초정밀 위치 제어를 위한 이중 서보 시스템의 보상기 설계 (Designing Compensators of Dual Servo System For High Precision Positioning)

  • 최현석;송치우;한창수;최태훈;이낙규;나경환
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2003년도 춘계학술대회
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    • pp.1309-1314
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    • 2003
  • The high precision positioning mechanism is used in various industrial fields. It is used in semiconductor manufacturing line, test instrument, Bioengineering, and MEMS and so on. This paper presents a positioning mechanism with dual servo system. Dual servo system consists of a coarse stage and a fine motion stage. The course stage is driven by VCM and the actuator of fine stage is the PZT. The purposes of dual servo system are stability, higher bandwidth, and robustness. Lead compensator is applied to this control system, and is designed by PQ method. Designed compensator can improve property of positioning mechanism.

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화합물 반도체 칩 생산을 위한 자원관리 시스템 개발 (Development of Resource Planning System for Compound Semiconductor Chip Manufacturing)

  • 나동길;박지훈;김동원
    • 한국경영과학회:학술대회논문집
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    • 대한산업공학회/한국경영과학회 2000년도 춘계공동학술대회 논문집
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    • pp.201-204
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    • 2000
  • 본 연구의 목적은 화합물 반도체를 생산하는 중소기업의 정보시스템을 설계하고 개발하여 적용하는데 있다. 제품의 수주에서 일정계획수립, 제품 재고관리 및 원·부자재 관리, 생산 가동율 등 생산활동전반에 걸친 업무 흐름을 분석하여 이에 사용되는 기초정보를 얻어내고, 이들 기반으로 관리자를 위한 관리정보와 의사결정자를 위한 경영정보를 Web상에 가시화 하는 시스템을 개발한다. 인터넷을 활용함으로써 기업 정보를 원격지에서 조회, 검색 할 수 있고 빠른 의사결정을 지원할 수 있도록 한다. 또한 기업 내부의 인트라넷 시스템과 연동하여 부서간 업무연락 및 정보시스템에서 발생하는 의사결정 요구사항을 쌍 방향으로 전달함으로써 그 활용도를 더욱 높인다. 본 시스템은 영업, 물류, 생산, 구매, 자재 인사, 회계 개발 등 기업 전체에 대한 자원관리를 위해 설계되었다. 개발된 시스템은 주문/수주정보관리, 제품재고관리, 원·부자재관리, 공정관리, 입출고 관리 등으로 구성되어 있다. 중소기업환경에 적합한 MS-SQL Server를 DB server로 사용하였고 Windows-NT기반의 ASP ( Active Server Page)를 사용하여 전 모듈을 개발함으로써 인터넷이 지원되는 모든 곳에서 접근 가능하도록 하였다.

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Microstage와 global stage를 결합한 초정밀 2축 이동장치 개발 (Development of high-precision 2-axis translation system comprised of microstage and global stage)

  • 김종윤;엄태봉
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.311-314
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    • 1997
  • According to the development of industrial equipment such as semiconductor manufacturing machines, optical device, and precision machine tool, a high-precision translation system with wide range has been required. This paper describes a high-precision 2-axis translation system, which consists of microstage and global stage. In order to achieve the highresolution in the long range, some engineering techniques are used. Three linear guides with flexible coupling are adopted to reduce the motor vibration in the global stage. A simple elastic hinge structure activated by five PZT is applied to reduce the angular dev~atlon. As the result of combination of microstage and global stage associated with some engineering techniques, the 2-axis translation system can measure the 200 X 200 mrn range with the nanometer accuracy.

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