• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2005.09a
• /
• pp.59-62
• /
• 2005

백색 LED 램프를 제조하는 공정에서 램프간의 전기적 개방상태의 절연상태를 유지하기 위해 사파이어 기판 위에 성장된 GaN 계 반도체 에피박막층을 제거하기 위해 유도 결합형 플라즈마 식각 공정을 이용하였다. 4 미크론의 두께를 갖는 GaN 층을 식각하는데 있어 식각 방지 마스킹 물질로 포토레지스트, $SiO_2,\;Si_{3}N_4$ 및 $Al_{2}O_3$를 시험하였다. 동일한 전력 및 가스유량상태에서 $Al_{2}O_3$만 에피층을 보호할 수 있음을 확인하였다.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.2
• /
• pp.32-37
• /
• 2016

Sidewall angle (SWA) of an absorber stack in extreme ultraviolet lithography mask is considered to be $90^{\circ}$ ideally, however, it is difficult to obtain $90^{\circ}$ SWA because absorber profile is changed by complicated etching process. As the imaging performance of the mask can be varied with this SWA of the absorber stack, more complicated optical proximity correction is required to compensate for the variation of imaging performance. In this study, phase shift mask (PSM) is suggested to reduce the variation of imaging performance due to SWA change by modifying mask material and structure. Variations of imaging performance and lithography process margin depending on SWA were evaluated through aerial image and developed resist simulations to confirm the advantages of PSM over the binary intensity mask (BIM). The results show that the variations of normalized image log slope and critical dimension bias depending on SWA are reduced with PSM compared to BIM. Process margin for exposure dose and focus was also improved with PSM.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.203-203
• /
• 2014

Due to the electrical properties such as narrow bandgap and high carrier mobility, indium antimonide (InSb) has attracted a lot of attention recently. For the fabrication of electronic or photonic devices, an etching process is required. However, during etching process, enegetic ions can induce structural damages on the bombarded surface. Especially, InSb has a very weak binding energy between In atom and Sb stom, it can be easily damaged by impingement of ions. In the previous work, to evaluate the surface properties after Ar ion beam etching, the plasma-induced structural damage on the etched InSb(100) surface had been examined by resonant Raman spectroscopy. As a result, we demonstrated the relation between the enhanced transverse optical(TO) peak in the Raman spectrum and the ion-induced structral damage near the InSb surface. In this work, the annealing effect on the etched InSb(100) surface has investigated. Annealing process was performed at $450^{\circ}C$ for 10 minute under antimony ambient. As-etched InSb(100) surface had shown a strongly enhanced TO scattering intensity in the Raman spectrum. However, the annealing process with antimony flowing caused the intensity to recover due to the structural reordering and the reduction of antimony vacancies. It proves that the origin of enhanced TO scattering is Sb vacancies. Furthermore, it shows that etching-induced damage can be cured effectively by the following annealing process under Sb ambient.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.5
• /
• pp.108-116
• /
• 1996

A semiconductor process imulator operated in windows$^{TM}$ environment has been developed. two-dimensional process simulation in personal computer has been enabled due to the improvement of CPU speed and the efficient use of memory. The process simulator in this paper is capable of calculating diffusion, oxidation, ion implantation, etching and deposition in two-dimensional manner. In addition, graphic-user-friendly editor, parser, and multi-dimensional graphical routine is also available in the devloped simulator.

• Journal of the Semiconductor & Display Technology
• /
• v.20 no.1
• /
• pp.59-63
• /
• 2021

Upper electrode is one of core parts using plasma etching process at semiconductor. The purpose of this study is to analyze effects of cutting conditions for mechanical machining of silicon upper electrode. For this research, surface roughness of machined workpiece and depth of damage inside of silicon electrode are experimented and analyzed and different values of feed rate and depth of cut are applied for the experiments. From these experiments, it is verified that the surface roughness and internal damaged layer get worse according to take more fast feed rate. In conclusion, cutting condition is very important factor for machining. Results of this study can use to develop various parts which are made from single crystal silicon and affect various benefits to the semiconductor industry for better productivity.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2004.05a
• /
• pp.92-96
• /
• 2004

Scales, accumulated on semiconductor equipment parts during device fabrication processes, often lower equipment lifetime and production yields. Thus, many equipments parts have be cleaned regularly. In this study, an attempt to establish an effective process for the removal of scales on the sidewall of collimators in the chamber of sputter is made. The EDX analysis revealed that the scales are composed of Ti and TiN with the colummar structure. It was found that the heat-treatment at 700 for 1 min. after the oxide removal in the HF solution, and then etching in the HNO3 : H2SO4 : H2O =4:2:4 solution for 5.5 hrs at 67 was the most effective process for the scale removal.

• Journal of IKEEE
• /
• v.19 no.4
• /
• pp.541-547
• /
• 2015

In current semiconductor manufacturing, as the feature size of integrated circuit (IC) devices continuously shrinks, detecting endpoint in plasma etching process is more difficult than before. For endpoint detection, various kinds of sensors are installed in semiconductor manufacturing equipments, and sensor data are gathered with predefined sampling rate. Generally, detecting endpoint is performed using OES data of by-product. In this study, OES data of both by-product and etchant gas are used to improve reliability of endpoint detection. For the OES data pre-processing, a combination of Signal to Noise Ratio (SNR) and Principal Component Analysis (PCA),are used. Polynomial Regression and Expanded Hidden Markov model (eHMM) technique are applied to pre-processed OES data to detect endpoint.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.472-472
• /
• 2011

The capacitive coupled plasma (CCP) has been extensively used in the semiconductor industry because it has not only good uniformity, but also low electron temperature. But CCP source has some problems, such as difficulty in varying the ion bombardment energy separately, low plasma density, and high processing pressure, etc. In this reason, dual frequency CCP has been investigated with a separate substrate biasing to control the plasma parameters and to obtain high etch rate with high etch selectivity. Especially, in this study, we studied on the etching of $SiO_2$ by using the pulse-time modulation in the dual-frequency CCP source composed of 60 MHz/ 2 MHz rf power. By using the combination of high /low rf powers, the differences in the gas dissociation, plasma density, and etch characteristics were investigated. Also, as the size of the semiconductor device is decreased to nano-scale, the etching of contact hole which has nano-scale higher aspect ratio is required. For the nano-scale contact hole etching by using continuous plasma, several etch problems such as bowing, sidewall taper, twist, mask faceting, erosion, distortions etc. occurs. To resolve these problems, etching in low process pressure, more sidewall passivation by using fluorocarbon-based plasma with high carbon ratio, low temperature processing, charge effect breaking, power modulation are needed. Therefore, in this study, to resolve these problems, we used the pulse-time modulated dual-frequency CCP system. Pulse plasma is generated by periodical turning the RF power On and Off state. We measured the etch rate, etch selectivity and etch profile by using a step profilometer and SEM. Also the X-ray photoelectron spectroscopic analysis on the surfaces etched by different duty ratio conditions correlate with the results above.

• Journal of Information Display
• /
• v.13 no.2
• /
• pp.61-66
• /
• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.2
• /
• pp.327-332
• /
• 2008

New RF matcher module has been proposed in this paper for improvement of RF matcher in plasma etcher system using in semiconductor and display panel manufacturing process. New designed warm gear was used instead of bevel gear in new driving module, and control system was re-arranged with one-chip micro-process technique. The matching performance of new match module was improved in various process condition with reduction of backlash and matching time, and flexible motion of motor compared commercial match module. However this new type RF match module will improve the productivity in etching process of the mass production line.