• Journal of the Semiconductor & Display Technology
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• v.5 no.3 s.16
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• pp.33-36
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• 2006

To produce a fine structure with uniform surface of barrier ribs in PDP, acid etching process has been used in manufacture process. It is necessary to understand the mechanism of etching, particularly on the interface of ceramic fillers and matrix glass. We investigated the effect of ceramic fillers (ZnO, $Al_2O_3$) on the microstructure of borate glass system to find an etching mechanism of barrier ribs. The barrier ribs was etched with several steps, dissolving a small amount of residual glass, taking out alumina fillers, and removing a cluster type of ZnO fillers and glass matrix.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.100-103
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• 2018

Due to the plasma applied from the outside, which acts as an etchant during the etching process, considerable heat is transferred to the wafer and a separate cooling process is performed to effectively remove the heat after the process. In this case, a direct cooling method using a refrigerant is suitable for cooling through effective heat exchange. The direct cooling method using the refrigerant using the latent heat exchange is superior to the cooling method using the sensible heat exchange. Therefore, in this paper, AMESim is used to design a direct refrigerant cooling system using latent heat exchange simulator was built.The constructed simulator is reliable compared with the actual experimental results. It is expected that this simulator will help to design and search for optimal process conditions.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.45-50
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• 2022

The etching with high selectivity of silicon dioxide over silicon nitride is essential in semiconductor fabrication, and gas phase etch (GPE) can increase the competitiveness of the selective dielectric etch. In this work, GPE of plasma enhanced chemical vapor deposited SiO₂ was performed, and the effects of process parameters, such as temperature, partial pressure ratio, and gas supply cycle, are investigated in terms of etch rate and within wafer uniformity. Employing multiple regression analysis, the importance of each parameter elements is analyzed.

• Journal of the Semiconductor & Display Technology
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• v.3 no.2
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• pp.11-15
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• 2004

Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.113-118
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• 2011

According to the high accuracy of semiconductor equipments, PCB substrate with much thin thickness is required. However, it is very difficult to sustain the PCB substrate without deformation in case of horizontal installation, due to low bending stiffness. In this research, new PCB process equipment with vertical installation has been developed in order to solve the problem of PCB substrate damage during etching process. As the main parts of etching system on PCB substrate, PCB substrate and JIG are analyzed through finite element method and experimental test. Through the analysis results of stress state, we could find the optimal JIG design to make the damage as low as possible.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.86.1-86.1
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• 2015

As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.415-418
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• 1996

Etching Process, one of the most important process in semiconductor fabrication, has input control part of which components are pressure, gas flow, RF power and etc., and plasma gas which is complex and not exactly understood is used to etch wafer in etching chamber. So this process has not real-time feedback controller based on input-output relation, then it uses EPD(End Point Detection) signal to determine when to start or when to stop etching. Various type EPD controller control etching process using EPD signal obtained from optical intensity of etching chamber. In development EPD controller we concentrate on compensation of this signal intensity and setting the relative signal magnitude at first of etching. We compensate signal intensity using neural network learning method and set the relative signal magnitude using fuzzy inference method. Potential of this method which improves EPD system capability is proved by experiences.

• Journal of the Semiconductor & Display Technology
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• v.2 no.3
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• pp.7-11
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• 2003

In this research, the etching characteristics of via contact and deep contact hole have been studied using multi-pole inductively coupled plasma(MICP) etching system. We investigated Plasma density of MICP source using the Langmuir probe and etching characteristics with RF frequency, wall temperature, chamber gap, and gas chemistry containing Carbon and Fluorine. As the etching time increases, formation of the polymer increases. To improve the polymer formation, we controlled the temperature of the reacting chamber, and we found that temperature of the chamber was very effective to decrease the polymer thickness. The deep contact etch profile and high selectivity(oxide to photoresist) have been achieved with the optimum mixed gas ratio containing C and F and the temperature control of the etching chamber.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.7-11
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• 2015

In order to protect the patterned mask from contamination during lithography process, pellicle has become a critical component for Extreme Ultraviolet (EUV) lithography technology. According to EUV pellicle requirements, the pellicle should have high EUV transmittance and robust mechanical property. In this study, silicon nitride, which is well-known for its remarkable mechanical property, was used as a pellicle membrane material to achieve high EUV transmittance. Since long silicon wet etching process time aggravates notching effect causing stress concentration on the edge or corner of etched structure, the remaining membrane is prone to fracture at the end of etch process. To overcome this notching effect and attain high transmittance, we began preparing a rather thick (200 nm) $SiN_x$ membrane which can be stably manufactured and was thinned into 43 nm thickness with HF wet etching process. The measured EUV transmittance shows similar values to the simulated result. Therefore, the result shows possibilities of HF thinning processes for $SiN_x$ EUV pellicle fabrication.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.9
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• pp.875-880
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• 2015

Traditional semiconductor process control has been performed through statistical process control techniques in a constant process-recipe conditions. However, the complexity of the interior of the etching apparatus plasma physics, quantitative modeling of process conditions due to the many difficult features constraints apply simple SISO control scheme. The introduction of the Advanced Process Control (APC) as a way to overcome the limits has been using the APC process control methodology run-to-run, wafer-to-wafer, or the yield of the semiconductor manufacturing process to the real-time process control, performance, it is possible to improve production. In addition, it is possible to establish a hierarchical structure of the process control made by the process control unit and associated algorithms and etching apparatus, the process unit, the overall process. In this study, the research focused on the methodology and monitoring improvements in performance needed to consider the process management of future developments in the semiconductor manufacturing process in accordance with the age of the APC analysis in real applications of the semiconductor manufacturing process and process fault diagnosis and control techniques in progress.