• Title/Summary/Keyword: Semiconductor etching process

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Notching Phenomena of Silicon Gate Electrode in Plasma Etching Process (플라즈마 식각공정에서 발생하는 실리콘 게이트 전극의 Notching 현상)

  • Lee, Won Gyu
    • Applied Chemistry for Engineering
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    • v.20 no.1
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    • pp.99-103
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    • 2009
  • HBr and $O_2$ in $Cl_2$ gas ambient for the high density plasma gate etching has been used to increase the performance of gate electrode in semiconductor devices. When an un-doped amorphous silicon layer was used for a gate electrode material, the notching profile was observed at the outer sidewall foot of the outermost line. This phenomenon can be explained by the electron shading effect: i.e., electrons are captured at the photoresist sidewall while ions pass through the photoresist sidewall and reach the oxide surface at a narrowly spaced pattern during the over etch step. The potential distribution between gate lines deflects the ions trajectory toward the gate sidewall. In this study, an appropriate mechanism was proposed to explain the occurrence of notching in the gate electrode of un-doped amorphous silicon.

Fabrication Method of Metal Grid Mesh Film Using the Gravure Offset Printing (그리비어 옵셋을 이용한 메탈 그리드 메쉬 필름 제작 기법)

  • Kim, Jung Su;Kim, Dong Soo
    • Journal of the Korean Society for Precision Engineering
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    • v.31 no.11
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    • pp.969-974
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    • 2014
  • Previously fabricated electronic devices were used for vacuum manufacturing processes such as conventional semiconductor manufacturing. However, they are difficult to apply to continuous processes such as roll-to-roll printing, which results in very high device manufacturing and processing costs. Therefore, many developers have been interested in applying continuous processes to contact printing or noncontact printing technologies and they proposed various continuous printing techniques instead of conventional batch coating. In this paper, we proposed improved gravure offset printing process as one of the contact printing technique. We used etching pattern geometry with soft core blanket roll for printing of ultra fine line below the 10um.Using this technique we obtained flexible metal grid mesh film as transparent conductive film.

Development of a multi-functional nano-fabrication system for fabrication and measurement (가공 및 측정이 가능한 복합나노가공시스템의 개발)

  • 장동영;박만진;김진현;한동철
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2004.04a
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    • pp.466-471
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    • 2004
  • In focused-ion-beam (FIB) application of micromachining and device transplantation, four kinds of FIB processes, namely FIB sputtering, FIB-induced etching, redeposition, and FIB-induced deposition, are well utilized. As with FIB systems, scanning electron microscopes(SEMs) were extensively used in the semiconductor industry. They are the tools of choice for defect review and providing the image resolution needed for process monitoring. The enhanced capabilities of a dual-column on one chamber system are quickly becoming realized by the nano industry for performing a wide range of application.

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Multi-Interval Discretization of Continuous-Valued Attributes for Constructing Incremental Decision Tree (증분 의사결정 트리 구축을 위한 연속형 속성의 다구간 이산화)

  • Baek, Jun-Geol;Kim, Chang-Ouk;Kim, Sung-Shick
    • Journal of Korean Institute of Industrial Engineers
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    • v.27 no.4
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    • pp.394-405
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    • 2001
  • Since most real-world application data involve continuous-valued attributes, properly addressing the discretization process for constructing a decision tree is an important problem. A continuous-valued attribute is typically discretized during decision tree generation by partitioning its range into two intervals recursively. In this paper, by removing the restriction to the binary discretization, we present a hybrid multi-interval discretization algorithm for discretizing the range of continuous-valued attribute into multiple intervals. On the basis of experiment using semiconductor etching machine, it has been verified that our discretization algorithm constructs a more efficient incremental decision tree compared to previously proposed discretization algorithms.

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Investigation of Curvature Effect on Planar InP/InGaAs Avalanche Photodiodes for Edge Breakdown Suppression (경계항복 억제를 위한 평판형 InP/InGaAs 애벌랜치 포토다이오드의 곡률 효과 분석)

  • 이봉용;정지훈;윤일구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.206-209
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    • 2002
  • With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

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The Optimization of Semiconductor Processes for MMIC Fabrication - Si$_3$N$_4$ deposition, GaAs via-hole dry etching, Airbridge process (MMIC 제작을 위한 반도체 공정 조건들의 최적화 - Si$_3$N$_4$증착, GaAs via-hole건식식각, Airbridge공정)

  • 정진철;김상순;남형기;송종인
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.934-937
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    • 1999
  • MMIC 제작을 위한 단일 반도체 공정으로써 PECVD를 이용한 Si₃N₄의 증착, RIE를 이용한 CaAs via-hole건식식각, 그리고 airbridge 공정조건을 위한 실험 및 분석 작업을 수행하였다. Si₃N₄의 증착 실험에서는 굴절률이 2인 조건을, GaAs via-hole 식각 실험에서는 최적화된 thru-via의 모양과 식각률을 갖는 조건을, airbridge 실험에서는 polyimide coating 및 건식 식각 조건과 금 도금 및 습식 식각의 최적 조건들을 찾아내었다.

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The Properties of Weakly Magnetized Planar Type Inductively Coupled $SF_6$ Plasma (자화된 평판형 유도 결합 $SF_6$ 플라즈마의 특성)

  • Yoon, Cha-Keun;Doh, Hyun-Ho;Whang, Ki-Woong
    • Proceedings of the KIEE Conference
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    • 1995.11a
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    • pp.438-440
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    • 1995
  • The impedance characteristics and plasma parameters were experimentally studied in a weakly magnetized planar type, inductively coupled plasma (ICP) system. Compared with non-magnetized for system higher power transfer efficiency, stable impedance matching, enhancement of plasma density and higher electron temperature can be obtained. Such improvements are mainly due to the excitation of deeply penetrating electromagnetic wave and reduction of radial loss of electrons. In particulary, $SF_6$ (sulfur hexafluride) plasma shows unstable impedance matching in non-magnetized ICP because electronegativity of $SF_6$ effects on plasma characteristics. But, magnetized inductively coupled $SF_6$ plasma shows enough impedance matching stability to be applicable to the polysilicon etching in semiconductor process.

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Non-Invasive Plasma Monitoring Tools and Multivariate Analysis Techniques for Sensitivity Improvement

  • Jang, Haegyu;Lee, Hak-Seung;Lee, Honyoung;Chae, Heeyeop
    • Applied Science and Convergence Technology
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    • v.23 no.6
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    • pp.328-339
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    • 2014
  • In this article, plasma monitoring tools and mulivariate analysis techniques were reviewed. Optical emission spectroscopy was reviewed for a chemical composition analysis tool and RF V-I probe for a physical analysis tool for plasma monitoring. Multivariate analysis techniques are discussed to the sensitivity improvement. Principal component analysis (PCA) is one of the widely adopted multivariate analysis techniques and its application to end-point detection of plasma etching process is discussed.

Soft Lithographic Approach to Fabricate Sub-50 nm Nanowire Field-effect Transistors

  • Lee, Jeong-Eun;Lee, Hyeon-Ju;Go, U-Ri;Lee, Seong-Gyu;Qi, Ai;Lee, Min-Hyeong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.410.1-410.1
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    • 2014
  • A soft-lithographic top-down approach is combined with an epitaxial layer transfer process to fabricate high quality III-V compound semiconductor nanowires (NWs) and integrate them on Si/SiO2 substrates, using MBE-grown ultrathin InAs as a source wafer. The channel width of the InAs nanowires is controlled by using solvent-assisted nanoscale embossing (SANE), descumming, and etching processes. By optimizing these processes, the NW width is scaled to less than 50 nm, and the InAs NWFETs has ${\sim}1,600cm^2/Vs$ peak electron mobility, which indicates no mobility degradation due to the size.

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A Study on Temperature Compensation of Silicon Piezoresistive Pressure Sensor (실리콘 저항형 압력센서의 온도 보상에 관한 연구)

  • 최시영;박상준;김우정;정광화;김국진
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.4
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    • pp.563-570
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    • 1990
  • A silicon pressure sensor made of a full bridge of diffused resistors was designed and fabricated using semiconductor integrated circuit process. Thin diaphragms with 30\ulcorner thickness were obtained using anisotropic wet chemical etching technique. Our device showed strong temperature dependence. Compensation networks are used to compensate for the temperature dependence of the pressure sensor. The bridge supply voltage having positive temperature coefficient by compensation networks was utilized against the negative temperature coefficient of bridge output voltage. The sensitivity fluctuation of pressure sensor before temperature compensation was -1700 ppm/\ulcorner, while it reduced to -710ppm\ulcorner with temperature compensation. Our result shows that the we could develop accurate and reliable pressure sensor over a wide temperature range(-20\ulcorner~50\ulcorner).

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