• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.733-740
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• 2014

A resistive micro Pirani gauge using amorphous silicon (a-Si) thin membrane is proposed. The proposed Pirani gauge can be easily integrated with the other process-compatible membrane-type sensors, and can be applicable for in-situ vacuum monitoring inside the vacuum package without an additional process. The vacuum level is measured by the resistance changes of the membrane using the low noise correlated double sampling (CDS) capacitive trans-impedance amplifier (CTIA). The measured vacuum range of the Pirani gauge is 0.1 to 10 Torr. The sensitivity and non-linearity are measured to be 78 mV / Torr and 0.5% in the pressure range of 0.1 to 10 Torr. The output noise level is measured to be $268{\mu}V_{rms}$ in 0.5 Hz to 50 Hz, which is 41.2% smaller than conventional CTIA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1850-1860
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• 1996

We present the results for the design ofantireflection (AR) coatings on facets of a multilayered structure waveguide device. The method, whose results agree very well with the reusults of the rigorous method in the case of a symmetric three layer structure deveice, is extended for the design of AR coatings on the facets of a multilayered structure waveguide device. the field profile in a multilayered structure waveguide necessary for the use of the extended method is obtained from the transfer matrix method. The virtual four layered structure method (VFLM) is proposed to reduce the time for the design ofAR coatings because the time for the design of AR coatings using the extended method increases as the number of layers increases. The optimum coating parameters and tolerance mapsfor two different six layered waveguide devices in Ref. [9] and [10] are obtained using the extendedmethod and the VFLM,and for the three different cases approximated as three layered waveguide devices to compare the results of each case. The results of the VFLM are similar to those of the extended methodcompared to those of the three layered structure waveguide. The main reason for the above results is that the field profile in the device calculated usingthe VFLM is similar to that calculated using the extended method compared to that for three layered structure wavegjide. We conclude that the extended method or VFLM should be used for the design of AR coatings on facets of a deice required for the facet reflectivity less than 10$^{-3}$ such as a semiconductor otical amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.88-94
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• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

• Korean Journal of Optics and Photonics
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• v.19 no.3
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• pp.219-223
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• 2008

To realize a widely tunable laser diode, a polymer coupled-ring reflector is hybrid- integrated with reflective semiconductor optical amplifier. Even though ring-ring and ring-bus coupling ratios are changed by fabrication errors in waveguide width and height, they remain very close to the single peak condition, ensuring high yield in fabrication. The tuning range is observed to be about 35 nm, maintaining the side mode suppression ratio of about 30 dB.

• Korean Journal of Optics and Photonics
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• v.22 no.3
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• pp.122-128
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• 2011

The AWG-filtering effect was investigated on a bidirectional 100-GHz-channel-spacing WDM-PON link using spectrum-sliced and RSOA-amplified light sources for downstream signals and a wavelength reuse technique for upstream signals. Signal performances of three different filtering AWGs, including Gaussian, trapezoidal, and rectangular types, were compared on link transmission with fiber nonlinear effects. As an extinction ratio of a downstream signal varied, the effect for both directional signals was analyzed and optimized. It was found that there was an optimal pass bandwidth of an AWG for the balance between relative intensity noise decrement and cross phase modulation noise increment as the bandwidth got wider.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• ETRI Journal
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• v.46 no.3
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• pp.550-563
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• 2024

A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of IKEEE
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• v.27 no.1
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• pp.45-52
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• 2023

Cold-junction correction(CJC) and disconnection detection circuit design of various thermocouples(TC) and multi-channel TC interface circuit using them were designed. The CJC and disconnection detection circuit consists of a CJC semiconductor device, an instrumentation amplifier(IA), two resistors and a diode for disconnection detection. Based on the basic circuit, a multi-channel interface circuit was also implemented. The CJC was implemented using compensation semiconductor and IA, and disconnection detection was detected by using two resistor and a diode so that IA input voltage became -0.42V. As a result of the experiment using R-type TC, the error of the designed circuit was reduced from 0.14mV to 3㎶ after CJC in the temperature range of 0℃ to 1400℃. In addition, it was confirmed that the output voltage of IA was saturated from 88mV to -14.2V when TC was disconnected from normal. The output voltage of the designed circuit was 0V to 10V in the temperature range of 0℃ to 1400℃. The results of the 4-channel interface experiment using R-type TC were almost identical to the CJC and disconnection detection results for each channel. The implemented multi-channel interface has a feature that can be applied equally to E, J, K, T, R, and S-type TCs by changing the terminals of CJC semiconductor devices and adjusting the IA gain.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.