• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of IKEEE
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• v.23 no.4
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• pp.1257-1264
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• 2019

A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.86-93
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• 2010

A system-on-chip (SoC) includes more functions and requires rapidly increased data bandwidth as the development of semiconductor process technology and SoC design methodology. As a result, the data bandwidth of on-chip-networks in SoCs becomes a key factor of the system performance, and the research on the on-chip-network is performed actively. Either AXI or OCP is considered to a substitute of the AHB which has been the most popular on-chip-network. However, they have much increased number of signal wires, which make it difficult to design the interface logic and the network hardware. The compatibility of the protocols with other protocols is not so good. In this paper, we propose a new interface protocol for on-chip-networks to improve the problems mentioned above. The proposed protocol uses less number of signal wires than that of the AHB and considers the compatibility with other interface protocols such as the AXI. According the analysis results, the performance of the proposed protocol per wire is much better than that of the AXI although the absolute performance is slightly inferior.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.8
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• pp.38-45
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• 2016

The objective of this research is to develop a method of improving MEP facility management based on 3D reverse engineering. Recently, 3D image scanning-based reverse engineering has been implemented in the fields of architecture, construction and (manufacturing). In the case where there are many objects and the MEP system is complicated, 3D reverse engineering is applied in semiconductor factories, because facility maintenance works cause the 2D drawing to be different from the original one. The 3D point cloud data obtained from 3D image scanning contains accurate data and can increase the efficiency of complicated MEP facility maintenance works. For this purpose, the present research studied the technology trends and analyzed the process of 3D reverse engineering. Based on the results, a method of improving MEP facility management is established and its effects described.

• Fire Science and Engineering
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• v.13 no.3
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• pp.19-26
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• 1999

$CO_2$ extinguishing system is the most $\phi$pular among the gas extinguishing system. $CO_2$ is usually stored with liquified state. But, it gasifies at the tip of nozzle when $CO_2$ was released through the pipe and head. A ro$\alpha$n temperature is very low when $CO_2$ was released. So electrical instrument, magnetic storage equipment and memory semiconductor are electrically or physically injured by cooling effect in a few minutes. So, we intend to find out temperature profile and electrical damage in compartment area, and supply basic d data for research and making standards and code through the full scale experiment. As result of experiment on the damage due to cooling effect from $CO_2$ extinguishing system, i instantaneous discharging temperature. was $-82.5^{\circ}C$ in average. An average temp. in the compartment after discharging $CO_2$ was $-40^{\circ}C$.

• Journal of Digital Convergence
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• v.9 no.2
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• pp.131-140
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• 2011

As the recent advances in network and wireless communications and semiconductor design and process technologies, our computing platform is rapidly shifting from desktop PCs to mobile devices such as UMPC (Ultra Mobile PC), Tablet PC, and Smartphone. Especially, wide-spreading Smartphones allow a new field of application based on location based services available with an user interface called augmented reality (AR). Therefore, this paper introduces an implementation of AR using various OpenAPls on Android Smartphones. In order to utilize enrich user data in real time, the system integrates with location based social network services also with OpenAPI. These APIs enable third-party developers to make use of rich contents of many portal web sites. The prototype was implemented on the real Android phone, Sky Sirius, and the result shows that it can provide an efficient location based service using AR technology without any constraints on mobile devices; in addition, it connects SNS to AR for sharing user data including photos, videos, and messages based on a specific location.

• Information Systems Review
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• v.11 no.2
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• pp.147-167
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• 2009

As global climate changes, the interest in environmental crisis is increasing and a number of international agreements and regulations against this crisis are being established. Global information technology(IT) corporations are building their own pro-environmental green IT strategies to cope with the regulatory measures. Green IT broadly refers to pro-environmental technologies designed to replace hazardous materials, maximize energy effectivity, and find alternative energies. In the current stage of the IT industry development, Green IT specifically refers to the technologies that deal with the server heat generation and the energy reduction in data center. This study defines the concept of Green IT and reviews its origin and necessity. Then, it examines the issues regarding Green IT industry in Korea as well as other countries and compares the Green IT strategies developed in each country. Reviewing the recent development of IT and data center market enables us to see that overall Green IT strategies focus on the establishment of Green Internet Data Centers. Therefore, this study analyzes the cases in which some domestic and foreign corporations introduced Green Data Centers in order to examine the protocol and legal requirements for building Green IT, the aspects of environmental evaluation and design, and specific strategies for launching Green IT strategies and its future assignments. The conclusions of this study are as follows. First, to introduce Green Data Center as a strategy to build Green IT, the government and corporations should cooperate with each other. Partial introduction at the initial stage is desirable because, through the process, mutual trust between the two parties can be built more smoothly. Second, CEO's determination to build Green IT and continue its operation is indispensable. CEO's are required to have clear understanding as to why Green IT needs to be built and how it should be constructed. Those who initiate the construction of Green Data Center for Green IT need to know the definition and necessity of Green IT while at the same time understanding the implicit meanings of Green IT. They also need to be aware of future-oriented values of Green Data Center and readjust their corporate business activities in the pro-environmental direction. Finally, not only the CEOs' pro-environmental activities but also the change of mind on the part of all corporate employees is required to realize Green IT. It should be remembered that pro-environmental Green IT starts with minor activities.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Clean Technology
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• v.21 no.2
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• pp.85-89
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• 2015

Utilized in a variety of electronic components, electronic components industry with metallic ink technology was established itself as a major technology research and development was gradually increasing, silver ink that is excellent in conductivity and stability, have long been used in the industry of electronic components in recent years and silver ink has been the size of nanoscale particles dispersed by developing display, an electronic tag, a flexible circuit board or the like used in the semiconductor and electronics as has been highlighted in, however industry modernization of equipment by increasing the production and consumption of products generated during the production process and environmental pollutants by use of waste products is expected to bring a serious environmental problem. In this study, prepared by a wet reduction method, the manufacturing process of the silver nano-ink to the entire process of the environmental impact assessment (LCA) was evaluated using the techniques. Life cycle assessment software GaBi 6 was used as received from the relevant agencies of the silver nano-ink data with reference to the manufacturing process, building inventory was international organization for standardization (ISO) 14040, 14044 compliant LCA conducted over four stages.