• 산업경영시스템학회지
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• 제39권1호
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• 대한산업공학회지
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• 제41권3호
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• pp.275-286
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• 2015

In this paper, we propose a practical method for setting up a daily production plan which can operate semiconductor fabrication factories more stably and linearly by determining work in process (WIP) targets and movement targets. We first adjust cycle times of the operations to satisfy the monthly production plan. Second, work in process (WIP) targets are determined to control the production progress of operations: earliness and tardiness. Third, movement targets are determined to reduce cumulated differences between WIP targets and actual WIPs. Finally, the determined movement targets are modified through a simulation model which considers capacities of the equipments and allocations of the WIPs in the fab. The proposed daily production planning method can be easily adapted to the memory semiconductor fabs because the method is very simple and has straightforward logics. Although the proposed method is simple and straightforward, the power of the method is very strong. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed daily production planning method will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1989년도 한국자동제어학술회의논문집; Seoul, Korea; 27-28 Oct. 1989
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• pp.421-426
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• 1989

Many of semiconductor manufacturing companies persuit automation of wafer fabrication to improve the yields and quality of their products. Development of real-time control system for wafer fabrication and wafer/cassette automatic transfer-system is the most important part to achieve the purpose. In this paper, SECS protocol proposed by SEMI is briefly reviewed and an implementation method of real-time monitoring and control system is suggested as one of the possible ways for wafer fabrication automation. The system consists of process equipments supporting SECS.

• 한국산업보건학회지
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• 제25권1호
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• pp.36-44
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• 2015

Objectives: This study aimed to elucidate the physicochemical properties of silica powder and airborne particles as by-products generated from fabrication processes to reduce unknown risk factors in the semiconductor manufacturing work environment. Materials and Methods: Sampling was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. Thirty-two powder and airborne by-product samples, diffusion(10), chemical vapor deposition(10), chemical mechanical polishing(5), clean(5), etch process(2), were collected from inner chamber parts from process and 1st scrubber equipment during maintenance and process operation. The chemical composition, size, shape, and crystal structure of silica by-product particles were determined by using scanning electron microscopy and transmission electron microscopy techniques equipped with energy dispersive spectroscopy, and x-ray diffractometry. Results: All powder and airborne particle samples were composed of oxygen(O) and silicon(Si), which means silica particle. The by-product particles were nearly spherical $SiO_2$ and the particle size ranged 25 nm to $50{\mu}m$, and most of the particles were usually agglomerated within a particle size range from approximately 25 nm to 500 nm. In addition, the crystal structure of the silica powder particles was found to be an amorphous silica. Conclusions: The silica by-product particles generated from the semiconductor manufacturing processes are amorphous $SiO_2$, which is considered a less toxic form. These results should provide useful information for alternative strategies to improve the work environment and workers' health.

• 한국시뮬레이션학회논문지
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• 제19권3호
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• pp.45-54
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• 2010

반도체 제조공정에 내재된 복잡성은 작업일정(job scheduling) 문제를 해석적 방법으로는 풀기 어렵기 때문에 보통 시스템 파라미터의 변화에 대한 효과를 이산사건 모델링 시뮬레이션에 의존하여 왔다. 한편 장비 고장 등 예측 불가능한 사건들은 고정된 작업일정 기법을 사용할 경우 전체 공정의 효율을 악화시킨다. 따라서 이러한 불확실성에 대해 최적의 성능을 내기 위해서는 작업일정을 실시간으로 대처 변경하는 것이 필요하다. 본 논문은 반도체 제조 공정에 대해 시스템 제어관점의 접근방법을 적용하여 이 문제에 적응형 실시간 작업제어 틀을 제안하고, DEVS 모델링 시뮬레이션 환경을 기반으로 제안된 틀을 설계 구현하였다. 제안된 방법은 기존의 임기응변적인 소프트웨어적인 방법에 비추어볼 때 전체 시스템을 이해하기 쉬우면서도 또한 추가되는 작업제어 규칙도 쉽게 추가 적용할 수 있는 유연성을 장점으로 가지고 있다. 여러 가지 실험결과 제안된 적응형 실시간 작업제어 프레임워크는 고정 작업규칙 방법에 비해 훨씬 나은 결과를 보여주어 그 효용성을 입증하였다.

• 산업공학
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• 제10권1호
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• pp.15-22
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• 1997

In semiconductor manufacturing, the probe process between fabrication and assembly process is constrained mostly by the equipment capacity because most products pass through the similar procedures. The probe process is usually performed in a batch mode with relatively short cycle times. The capability of the probe process can be determined by the optimal combination of the equipments and the products. A probe line usually has several types of equipment with different capacity. In this study, the probe line is modeled in terms of capacity to give the efficient planning and control procedure. For the practical usage, the hierarchical capacity planning procedure is used. First, a monthly capacity plan is made to meet the monthly production plan of each product. Secondly, the daily capacity planning is performed by considering the monthly capacity plan and the daily fabrication output. Simple heuristic algorithms for daily capacity planning are developed and some experimental results are shown.

• 전자통신동향분석
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• 제38권6호
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• 한국경영과학회지
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• 제18권1호
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• pp.119-126
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• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

• 대한안전경영과학회지
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• 제6권4호
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• 반도체디스플레이기술학회지
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• 제5권4호
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• pp.29-34
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• 2006

In order to design an OLED(Organic Luminescent Emitting Device) evaporation system, geometric simulation of film thickness distribution profile is required. For the OLED evaporation process, thin film thickness uniformity is of great practical importance. In this paper, a geometric modeling algorithm is introduced for process simulation of the OLED evaporating process. The physical fact of the evaporating process is modeled mathematically. Based on the developed method, the thickness of the thin-film layer can be successfully controlled.