• Journal of Information Technology Services
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• v.8 no.4
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• pp.165-174
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• 2009

This paper outlines opportunities and challenges in the implementation of BPEL based WFMS(WorkFlow Management System) for the MES(Manufacturing Execution Systems) in semiconductor manufacturing. At present, the most MESs in semiconductor wafer fabrication shop have the problems in terms of application software integration, reactivity, and adaptability. When a plant has to produce new product mix, remodel the manufacturing execution process, or replace obsolete equipments, the principal road blocks for responding to new manufacturing environment are the difficulties in porting existing application software to new configurations. In this paper, the issues about WFMS technologies including BPEL standard applied for MES are presented. And then, we introduce the integrated development framework named nanoFlow which is optimized for developing the BPEL based WFMS application for automated manufacturing system. And we describe a WFMS implemented with using nanoFlow framework, review and evaluate the system.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.10-13
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• 2006

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-Sic/SOI pressure sensor presents a high-sensitivity and excel lent temperature stability.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.14-17
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• 2006

This paper describes a novel processing technique for fabrication of polymer-derived SiCN (silicone carbonitride) microstructures for super-temperature MEMS applications. PDMS (polydimethylsiloxane) mold is fabricated on SU-8 photoresist using standard UV photolithographic process. Liquid precursor is injected into the PDMS mold. Finally, solid polymer structure is cross-linked using HIP (hot isostatic pressure) at $400^{\circ}C$, 205 bar Optimum pyrolysis and anneal ins conditions are determined to form a ceramic microstructure capable of withstanding over $1400^{\circ}C$. The fabricated SiCN ceramic microstructure has excel lent characteristics, such as shear strength (15.2 N), insulation resistance ($2.163{\times}10^{14}\;{\Omega}$) and BDV (min. 1.2 kV) under optimum process condition.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.170-173
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• 2006

Ferroelectric $Bi_{3.35}Sm_{0.65}Ti_3O_{12}(BST)$ thin films were deposited on $Pt(111)/Ti/SiO_2/Si(100)$ substrates by a sol-gel spin-coating process. In this experiments, $Bi(TMHD)_3$, $Sm_5(O^iPr)_{13}$, $Ti(O^iPr)_4$ were used as precursors, which were dissolved in 2-methoxyethanol. Thereafter, the thin films with the thickness, of 240nm were annealed from 600 to $720^{\circ}C$ in oxygen atmosphere for 1 hr, and post-annealed in oxygen atmosphere for 1 hr after deposition of Pt electrode to enhance the electrical properties. The remanent polarization and coercive voltage of the BST thin films annealed at $720^{\circ}C$ were $19.48\;{\mu}C/cm^2$ and 3.40 V, respectively, and a fatigue-free characteristics. As a result, Sm-substituted bismuth titanate films with good ferroelectric properties and excellent fatigue resistance are useful candidates for ferroelectric memory applications.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.179-182
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• 2007

Polycrystaline (poly) 3C-SiC thin film on n-type and p-type Si were deposited by APCVD using HMDS, $H_2$, and Ar gas at $1180^{\circ}C$ for 3 hour. And then the schottky diode with Au/poly 3C-Sic/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) value were measured as 0.84 V, over 140 V, 61nm, and $2.7{\times}10^{19}\;cm^3$, respectively. The p-n junction diode fabricated by poly 3C-SiC was obtained like characteristics of single 3C-SiC p-n junction diode. Therefore, its poly 3C-SiC thin films are suitable MEMS applications in conjuction with Si fabrication technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.117-122
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• 2001

In this paper, we report on photoelectrochemical etching process of 6H-SiC semiconductor wafer. The etching was performed in two-step process; anodization of SiC surface to form a deep porous layer and thermal oxidation followed by an HF dip. Etch rate of about 615${\AA}$/min was obtained during the anodization using a dilute HF(1.4wt% in H$_2$O) electrolyte with the etching potential of 3.0V. The etching rate was increased with the bias voltage. It was also found out that the adition of appropriate portion of H$_2$O$_2$ into the HF solution improves the etching rate. The etching process resulted in a higherly anisotropic etching characteristics and showed to have a potential for the fabrication of SiC devices with a novel design.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.3
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• pp.11-17
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• 1978

A medium scale integrated circuit, BCD to seven segment decoder/driver is designed and fabricated by employing P-channel metal-oxide-semiconductor technology. The device configuration is specifically designed for a common cathode seven segment LED display unit. The decoder logic is composed of two serially connected read-only-memory matrices and the LED drivers are implemented with wide channel FET's. The fabricated integrated circuit performed successfully with a supply voltage between -7 Volt and -26 Volt and the non-uniformity of the LED segment current is about 10%.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.37-42
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• 2009

The performance of an OLED(organic luminescent emitting device) fabrication system strongly depends on the design of the evaporation cell-source. Trends in display sizes have hauled the enlargement of mother glass substrates. The enlargement of substrates requires the improvement and the enlargement of the effusion cell-source for OLED evaporation process. The deposited layers should be as uniform as possible, and therefore it is important to know the effusion profile of the molecules emitted from the cell-source. Conventional 2D DSMC algorithm cannot be used for simulating the new concept cell-source design, such as a linear source. This work concerns the development of 3D DSMC (direct simulation Monte Carlo) analysis for simulating the behavior of the evaporation cell-sources. In this paper, the 3D DSMC algorithm was developed and the film thickness profiles were obtained by the numerical analysis.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.183-192
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• 2001

1- Buildup PCB technology is utilized to a bare chip attach substrate technology for packaging of semiconductor chip 2- Requirement for the substrate design rule is described in SIA International Technology Roadmap for Semiconductor. 3- There are seven fabrication methods of build-up technology. 4- Coating and lamination for resin and photo, and laser for micro via hope processes are available. Below $50\mu\textrm{m}$ in diameter is possible. 5- Fine pitch lines down to $30\mu\textrm{m}$ can be achieved by pattern plating with better electrical property. 6- Dielectric loss reduction is a key material improvement item for next generation build-up technology. 7- High band width up to 512 GB/s is possible with current wiring groundrule.