• Journal of Korean Institute of Industrial Engineers
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• v.36 no.1
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.38-41
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• 2019

Proton beam writing is a direct writing lithography technique for semiconductor fabrication process. The advantage of this technique is that the proton beam does not scatter as they travel through the matter and therefore maintain a straight path as they penetrate into the resist. The experiment has been carried out at Accelerator Mass Spectrometry facility. The focused proton beam with the fluence of $100nC/mm^2$ was exposed on the PMMA coated silicon sample to make a pattern on a photo resist. The results show the potential of proton beam writing as an effective way to produce semiconductor fabrication process.

• Journal of the Korea Society for Simulation
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• v.15 no.2
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• pp.51-57
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• 2006

Production environment of semiconductor industry is shifting from 200mm wafer process to 300mm wafer process. In the new era of semiconductor industry, FAB (fabrication) Line Automation is a key issue that semiconductor industry is facing in shifting from 200mm wafer fabrication to 300mm wafer fabrication. In addition, since the semiconductor manufacturing technologies are being widely spread and market competitions are being stiffened, cost-down techniques became basis of growth. Most companies are trying to reduce average cycle time to increase productivity and delivery time. In this paper, we simulated 300mm wafer fabrication semiconductor manufacturing process by laying great emphasis on reduce average cycle time.

• IE interfaces
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• v.22 no.1
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• pp.73-84
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• 2009

In this paper, we propose a dispatching algorithm for constructing a Factory Operating System (FOS) which can operate semiconductor fabrication factories more efficiently and effectively. We first define ten dispatching criteria and propose two methods to apply the defined dispatching criteria sequentially and simultaneously (i.e. fixed dispatching architecture). However the fixed type methods cannot apply the criteria adaptively by considering changes in the semiconductor fabrication factories. To overcome this type of weakness, an adaptive dispatching architecture is proposed for applying the dispatching criteria dynamically based on the factory status. The status can be determined by combining evaluation results from the following three status criteria; target movement, workload balance, and utilization rate. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed adaptive dispatching architecture will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.

• IE interfaces
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• v.16 no.3
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.26 no.3
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• pp.67-73
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• 2003

Manufacturing technologies of compound semiconductor are similar to the process of memory device, but management technology of manufacturing process for compound semiconductor is not enough developed. Semiconductor manufacturing environment also has been emerged as mass customization and open foundry service so integrated manufacturing system is needed. In this study we design the integrated manufacturing system for compound semiconductor fabrication t hat has monitoring of process, reduction of lead-time, obedience of due-dates and so on. This study presents integrated manufacturing system having database system that based on web and data acquisition system. And we will implement them in the actual compound semiconductor fabrication.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.153-161
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• 2016

Semiconductor manufacturing has suffered from the complex process behavior of the technology oriented control in the production line. While the technological processes are in charge of the quality and the yield of the product, the operational management is also critical for the productivity of the manufacturing line. The fabrication line in the semiconductor manufacturing is considered as the most complex part because of various kinds of the equipment, re-entrant process routing and various product devices. The efficiency and the productivity of the fabrication line may give a significant impact on the subsequent processes such as the probe line, the assembly line and final test line. In the management of the re-entrant process such as semiconductor fabrication, it is important to keep balanced fabrication line. The Performance measures in the fabrication line are throughput, cycle time, inventory, shortage, etc. In the fabrication, throughput and cycle time are the conflicting performance measures. It is very difficult to achieve two conflicting goal simultaneously in the manufacturing line. The capacity of equipment is important factor in the production planning and scheduling. The production planning consideration of capacity can make the scheduling more realistic. In this paper, an input and scheduling rule are to achieve the balanced operation in semiconductor fabrication line through equipment capacity and workload are proposed and evaluated. New backward projection and scheduling rule consideration of facility capacity are suggested. Scheduling wafers on the appropriate facilities are controlled by available capacity, which are determined by the workload in terms of the meet the production target.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1105-1106
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• 2008

Staggered type self-aligned transparent-oxide-semiconductor transistors with indium-zinc-oxide as a semiconductor have studied. In this device fabrication, successive sputtering of oxide semiconductor and insulator without breaking of vacuum and without exposing in air, humidity and oxygen can be realized because oxide semiconductor is transparent. As a result of fabrication, transistor characteristics with mobility of $30cm^2/Vs$ and on-off ratio of $10^5$ could be obtained for the newly developed self-alignment device structure.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.3
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• pp.443-451
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• 2001

This paper addresses an on-line scheduling method for track systems in semiconductor fabrication. A track system is a clustered equipment performing photolithography process in semiconductor fabrication. Trends toward high automation and flexibility in the track systems accelerate the necessity of the intelligent controller that can guarantee reliability and optimize productivity of the track systems. This paper proposes an-efficient on-line scheduling method that can avoid deadlock inherent to track systems and optimize the productivity. We employ two procedures for the on-line scheduling. First, we define potential deadlock set to apply deadlock avoidance policy efficiently. After introducing the potential deadlock set, we propose a deadlock avoidance policy using an on-line Gantt chart, which can generate optimal near-optimal schedule without deadlock. The proposed on-line scheduling method is shown to be efficient in handling deadlock inherent to the track systems through simulation.