• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• The Magazine of the IEIE
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• v.35 no.7
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• pp.57-71
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• 2008

The last decade has witnessed great improvements in power semiconductor devices thanks to the advanced design and process, which have made it possible to significantly improve the electrical performances of electronic systems while simultaneously reducing their site, weight and perhaps most importantly reducing their cost. Among the power semiconductor devices, IGBT will be a key semiconductor component for power industry since it has a huge potential to cover large areas of power electronics from small home appliances to heavy industries. Currently, only a few limited power semiconductor manufacturers supply most of the industrial consumptions of power IGBT and its modules. Therefore, a large portion of technology in the power industry is dependent on other advanced countries. In this regard, to independently build power IGBT devices and the relevant power module technology, Korean government initiated a new 5-year project 'Power IT,' which also aimed at booming the business of the power semiconductor and the allied industries. With the success of this power IT project, it is expected that the power semiconductor technology will be a basis to foster the high power semiconductor industry and moreover, there will be more innovative developments in the Korea region and globally Also, forming the channel between the customers and suppliers, it is possible to effectively develop the customized power products, which could strengthen the competitiveness of Korean power industry. Furthermore, the power industry including semiconductor manufacturers will be technologically self-supporting and be able to obtain good business opportunities, and eventually increase the share in the growing power semiconductor market, which could be positioned as a major industry in Korea.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.158-162
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• 2002

This paper presents a novel 3-phase IGBT module called the SPM (Smart Power Module). This is a new design developed to provide a very compact, low cost, high performance and reliable motor drive system. Several distinct design concepts were used to achieve the highly integrated functionality in a new cost-effective small package. An overall description to the SPM is given and actual application issues such as electrical characteristics, circuit configurations, thermal performance and power ratings are discussed

• Korean Journal of Computational Design and Engineering
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• v.19 no.4
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• pp.402-409
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• 2014

Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.

• Design & Manufacturing
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• v.16 no.1
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• pp.15-20
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• 2022

This paper is about elimination the situation in which gas sensor data becomes inaccurate due to temperature control when a semiconductor gas sensor is driven. Recently, interest in semiconductor gas sensors is high because semiconductor sensors can be driven with small and low power. Although semiconductor-type gas sensors have various advantages, there is a problem that they must operate at high temperatures. First temperature control was configured to adjust the temperature value of the heater mounted on the gas sensor. At that time, in controlling the heater temperature, gas sensor data are fluctuated despite supplying same gas concentration according to the temperature controlled. To resolve this problem, gas and temperature are extracted as a data. And then, a relation function is constructed between gas and temperature data. At this time, it is included low pass filter to get the stable data. In this paper, we can find optimal gain and parameters between gas and temperature data by using genetic algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Korean Journal of Computational Design and Engineering
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• v.13 no.4
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• pp.273-285
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• 2008

In this paper we propose an engineering bill of materials (E-BOM) copy method that can be utilized to manage the product information for each equipment during building a product lifecycle management (PLM) system in the order-specific semiconductor equipment manufacturer. The previous works studied on an E-BOM creation and management method for the mass manufacturing and production. The method is difficult to apply to an environment in which many engineering changes occur and the different specification to each equipment is required such as semiconductor equipments and facilities adopting built-to-order instead of built for inventory. Moreover the method is known to be the major drawback to deteriorate the design efficiency. Our E-BOM copy method enables users efficiently to manage the specification of a product and shortens the product development cycle. To implement the E-BOM copy method in the PLM environment, we developed the E-BOM copy system that automatically generates new parts and their numbers according to the numbering rule while copying the E-BOM from existing semiconductor equipments and then can apply the parts for reuse to new semiconductor equipments. This system can duplicate not only 3D CAD data but also technical documents.

• Korean Journal of Materials Research
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• v.19 no.5
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.34-39
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• 2017

Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The first process for the manufacturing of the semiconductor wafers is the ingot growing. The vibrations are supposed to be the most important factors for the ingot quality. In order to maintain the ingot quality, the growers have the automatic shut-down equipments which are activated by vibrations, and are sensitive enough to react to the earthquakes generated in Japan. In this study, the structure of an ingot grower was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

• Journal of IKEEE
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• v.27 no.1
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• pp.65-70
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• 2023

More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and various CNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductor chip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discusses a methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAM or CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM and compare its performance with the conventional MOSFET SRAM and CNTFET SRAM.