• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.4
• /
• pp.221-228
• /
• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• Transactions on Electrical and Electronic Materials
• /
• v.15 no.3
• /
• pp.149-154
• /
• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.22 no.3
• /
• pp.356-363
• /
• 2013

Mechanical molding press which is used for transformation process during semiconductor manufacturing process has structural deformations by pressure. If these deformations have over limit range, life of the press itself can be reduced and it will be exerted on a bad effect for quality of the semiconductor. In this research, the main plates and links of a press are analyzed in relation to the structural deformations caused by pressure excluding thermal deformations. After modifying the modeling, the analysis is performed again to determine optimal design of the press, and this design is introduced to ensure that most of the stresses on the main plates are within safe allowable limits. As a result, an optimal design method for the structure is investigated to produce the desired pressure even when the size of the main structure is minimized.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.26 no.3
• /
• pp.67-73
• /
• 2003

Manufacturing technologies of compound semiconductor are similar to the process of memory device, but management technology of manufacturing process for compound semiconductor is not enough developed. Semiconductor manufacturing environment also has been emerged as mass customization and open foundry service so integrated manufacturing system is needed. In this study we design the integrated manufacturing system for compound semiconductor fabrication t hat has monitoring of process, reduction of lead-time, obedience of due-dates and so on. This study presents integrated manufacturing system having database system that based on web and data acquisition system. And we will implement them in the actual compound semiconductor fabrication.

• Journal of the Korean Society of Industry Convergence
• /
• v.15 no.1
• /
• pp.37-42
• /
• 2012

Trends in semiconductor equipment industry are to reduce the cost of producing semiconductor, semiconductor process development, facility development, and the minimum investment in terms of cost and quality. Semiconductor equipments are being considered to review and development is proceeding at the same time. In the first part of the semiconductor assembly process, in which the importance of die bonding process is emerging, a wide leadframe type die bonding machine is demanded for productivity. Die bonding machine was designed through experiments and by trial and error. It costs a lot of time and financial burden. The purpose of this study is to solve these problems by using the CAE tool 3G. By using finite element method, thermal analysis of die bonding machine to the various widths leadframe die bonder machine rail is performed for design.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.4
• /
• pp.71-76
• /
• 2010

According to recent changes in industry for semiconductor devices, a low-temperature treatment has become a necessity. These changes relate to size refinement and the development of new materials. While variation in cooling efficiency does not affect the yield when using a high-temperature treatment, uniform cooling efficiency is necessary avoid "inconsistencies/bends" in low temperature treatments. However it is difficult to increase temperature stabilization in low temperature treatments. In this paper, using CFD (Computer Fluid Dynamics), we analyze and manipulate the design and input of the low-temperature system to attempt to control for temperature variations within the quartz tube, of which airflow appears to be a predominant factor. This simulation includes variable inputs such as airflow rate, head pressure, and design manipulations in the S.C.U. (Super Cooling Unit).

• Proceedings of the KIEE Conference
• /
• 1987.07a
• /
• pp.403-406
• /
• 1987

CMOS operational amplifier is most useful building bloch in analog circuit. This paper represents the analysis and design method of CMOS OP AMP to use general purpose such as the A/D and D/A converter, PCM encoder and decoder etc. The required specifications is obtained by changing W/L ration of CMOS devices. The design procedure must be iterative in as much as it is almost impossible to relate all specifications simultaneously. This is performanced with IBM-PC XT by using SPICE(SIMULATION PROGRAM WITH INTEGRATED CIRCUIT EMPHASIS)program.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.1
• /
• pp.62-66
• /
• 2022

Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.286-289
• /
• 2000

PHEMT's with three different doping structures, -SH(single-heterojunction), DH (double-heterojunction), and DC(doped-channel)-,were designed, fabricated and characterized to study the effect of doping layer structures on the performance of millimeter-wave PHEMT's. 0.25${\mu}{\textrm}{m}$ DH-PHEMT with below-channel doping of 1$\times$10$^{12}$ c $m^{-2}$ was superior to SH-PHEMT by 40％ in $I_{dss}$, 20％ in f/sib T/ and showed broador gm- $I_{D}$ characteristics which is advantageous to power applications DH-PHEMT showed similar DC and small-signal performance compared with DC-PHEMT. Taking the much higher carrier mobility into considerations, DH-PHEMT is believed to be the best candidate for millimeter-wave, low-noise and/or power applications.s.s.

• Fire Science and Engineering
• /
• v.14 no.4
• /
• pp.23-28
• /
• 2000

A performance-based design of smoke management systems for semiconductor fabrication facilities is described in this paper. The example of one such facility is discussed. Performance criteria for smoke control systems were established, effective smoke removal system features were identified and optimal system exhaust capacity requirements were developed by applying engineering tools including Fire Dynamic Simulator model. Considering the fact that the absence of relevant design guide, codes for consensus standards for semiconductor smoke design in Korea and United States this performance based approach can and should be applied to other fabrication facilities designs.