• 한국광학회지
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• 제7권3호
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• pp.287-294
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• 1996

MOCVD(metal-organic chemical vapour deposition)방법으로 성장시킨 이중 이종접합구조 GaAs/AlGaAs 웨이퍼를 이용하여 광위상변조기를 제작하였다. 제작과정에서 도파로와 절연층의 형성시 동일 포토레지스트 패턴을 이용하는 자기종렬공정을 개발하여 그 효용성을 입증하였다. Fabry-Perot 간섭법을 이용하여 변조기의 위상변조효율을 측정하였으며 1.31.mu.m파장에서 TE 편광의 경우 22.5.deg./Vmm의 위상변조특성을 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.853-858
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• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

• 대한전자공학회논문지
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• 제23권6호
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2001년도 High Temperature Superconductivity Vol.XI
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• pp.33-33
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• 2001

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.8.1-8.1
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• 2009

The self-assembly of peptide-based building blocks into nanostructures is an attractive route for fabricating novel materials because of their capacity for molecular recognition and functional flexibility as well as the mild conditions required in the fabrication process. Among various peptide-based building blocks forming nanostructures, the simplest building blocks are aromatic dipeptides like diphenylalanine, which can readily self-assemble into nanotubes in aqueous solutions at ambient conditions. Recently, we have developed a high-temperature solid-phase self-assembly process for diphenylalanine. Through this novel process, we succeeded in the growth of vertically well-aligned, uniform nanowires from amorphous peptide thin film. To demonstrate the versatility of our approach, we also fabricated a micropattern of peptide nanowires by combining our solid-phase growth method and simple soft lithographic techniques. We believe that our studies on peptide self-assembly will provide a new horizon for peptide-based nanofabrication.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.261-264
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• 2007

We developed a non self-aligned poly-silicon TFTs fabrication process at two different temperatures on spin-coated polyimide layer above Si-wafer. After TFTs fabrication, the polyimide layer was mechanically released from the Si-wafer and the devices characteristics were compared. In addition self-heating and hot-carrier induced instabilities were analysed.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 춘계학술대회논문집
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• pp.434-438
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• 2003

The shearing process for the sheet metal is normally used in the precision elements such as semi-conductor components. In these precision elements, the burr formation brings a bad effect on the system assembly and demands the additional de-burring process. In this paper, we have developed the desktop-type precision punching system to investigate the burr formation mechanism and present kinematically Punch-die auto aligning methodology, for the purpose of burr unifomizing and minimizing, between the rectangular shaped punch and die. By using the scanning electron microscope, the aligned punching results are compared with the miss-aligned ones. Also, we measured the relative burr heights using the self-designed laser measuring device for insitu self aligning. Since it is hard to get the perfect, so called, burr-free edges during the shearing process, we introduced the ultrasonic do-burring machine. The de-burring operation was carried out by a novel do-burring method, the reversal flow resistance method, under different machining loads and abrasive types. The final do-burring results show the validity of our punching do-burring system pursuing the burr-free punched elements.

• 전자공학회논문지A
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• 제33A권7호
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• 전기학회논문지
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• 제56권4호
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• pp.773-776
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• 2007

A microstructure array has been proposed for micro plasma generation using electroplating and double exposed process. A stable atmospheric plasma has been generated at a low voltage by utilizing the micro electrode gap. Self-aligned microstructure can provide uniform electrode overlap with precisely controlled gap between the electrodes. The proposed structure allows for triode operation, which can expand the generated plasma over a large area by applying a lateral electric field. Electrical characteristics of the micro triode confirm the large numbers of the plasma ions are drifted to the secondary cathode by the lateral electrical field.