• 대한전자공학회논문지TE
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• 제37권3호
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• pp.1-5
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• 2000

A waveguide of coupled optical modulator was fabricated on LiNbO$_3$ based on proton exchange with self-aligned thin film electrode method. The electrode pattern was designed using a self-aligned method. After proton exchange process, the waveguide was prepared by annealing process. The initial crossover state of the fabricated 2$\times$2 coupled optical modulator was observed with controlling the annealing process variables and the structure of self-aligned thin film electrodes. It was shown form the present work that the measured crosstalk is -29.5[dB] and 8.0[V] of detected modulating voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.783-786
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• 2003

A simple fabrication method of self-aligned ridge waveguides with dielectric side buffers is demonstrated on +Z- cut LiNbO$_3$. The ridge waveguide is fabricated by a combination of the annealed proton exchange process and the proton-exchanged wet etching technique. The self-aligned process is achieved by wet etching of aluminum.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1841-1851
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• 1990

Self-aligned gate GaAs MESFETs using ion beam deposited tungsten applicable to GaAs LSI fabrication process have been fabricated. Silicon implanted samples were annealed using isothermla two step RTA process and conventional one step RTA process. The electrical and physicla characteristics of annealed samples were investigated using Hall and I-V measurements. As results of measurements, activation characteristics of the isothermal two step RTA process are better than those of one step annealed ones. Using the developed processes, GaAs SAFETs (Self-Aligned Gate FET) have been fabricated and electdrical characteirstics are measured. As results, subthreshold currents of SAGFETs are 6x10**-10 A/\ulcorner, that is compatible to conventional MESFET, maximum transconductances of 0.75\ulcorner gate MESFET using one step RTA process and 2\ulcorner gate MESFET using isothermal two step RTA process are 18 mS/mm, 41 mS/mm respectively.

• E2M - 전기 전자와 첨단 소재
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• 제8권4호
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• pp.443-450
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• 1995

A directional coupler which on the X-cut $LiNbO_3$ substrate is fabricated by using proton exchange method and self-aligned method. After proton exchange process, the waveguide is formed by annealing process. The relation ship between refractive index change of waveguide and maximum output was studied along with the annealing time. A self-aligned method was used to simplify the fabrication process of the waveguide and to maximize the efficiency of electric field. The on-off state of modulator has been observered with the switching of the directional coupler by the electric field effect and also the switching voltage of the directional coupler has been measured with 8.0 [V].

• 전자공학회논문지D
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• 제35D권7호
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• pp.88-93
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• 1998

For the self-aligned AlGaAs/GaAs HBTs, the surface states at the interface between the extrinsic base surface and the passivation nitride is a major cause of degradation of dc characteristics. In this paper the degradation mechanisms of self-aligned AlGaAs/GaAs HBT were analyzed, and GaAs HBTs, which employed an InGaP ledge emitter structure formed by the nonself-aligned process to cover the surface of the extrinsic base and reduce the surface states, produced high reliability. Accoridng to the acceleration lifetime test, the nonself-aligned InGaP/GaAs HBTs produced very reliable dc characteristics comparing with the self-aligned AlGaAs/GaAs HBTs. The activation energy was 1.97eV and MTTF $4.8{\times}10^{8}$ hrs at $140^{\circ}C$ which satisfied the MIL standard.

• 전자공학회논문지A
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• 제32A권5호
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 한국정밀공학회지
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• 제25권8호
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• pp.17-20
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• 2008

• 전자공학회논문지A
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• 제32A권2호
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.303-306
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• 2005

We report the self-aligned low temperature poly silicon (LTPS) TFT process using simple doping process. In conventional LTPS-TFT, the Lightly Doped Drain (LDD) doping and source/drain doping are processed separately by aligning the gate with the source and drain during the gate lithography step. This ne w process not only fabricates fully self-aligned low temperature poly silicon TFTs with symmetric LDD structure but also simplifies the process flow with combined source/drain doping and LDD doping in one step. LDD doping process can be achieved using only source/drain doping process according to the new structure. In this paper, the TFT characteristics of NMOS and PMOS using the new doping process will be discussed.