• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.4
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• pp.843-859
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• 2024

The university course scheduling problem (UCSP) aims at optimally arranging courses to corresponding rooms, faculties, students, and timeslots with constraints. Previously, the university staff solved this thorny problem by hand, which is very time-consuming and makes it easy to fall into chaos. Even some meta-heuristic algorithms are proposed to solve UCSP automatically, while most only utilize one single algorithm, so the scheduling results still need improvement. Besides, they lack an in-depth analysis of the inner algorithms. Therefore, this paper presents a novel and practical approach based on Tabu search and simulated annealing algorithms for solving USCP. Firstly, the initial solution of the UCSP instance is generated by one construction heuristic algorithm, the first fit algorithm. Secondly, we defined one union move selector to control the moves and provide diverse solutions from initial solutions, consisting of two changing move selectors. Thirdly, Tabu search and simulated annealing (SA) are combined to filter out unacceptable moves in a parallel mode. Then, the acceptable moves are selected by one adaptive decision algorithm, which is used as the next step to construct the final solving path. Benefits from the excellent design of the union move selector, parallel tabu search and SA, and adaptive decision algorithm, the proposed method could effectively solve UCSP since it fully uses Tabu and SA. We designed and tested the proposed algorithm in one real-world (PKNU-UCSP) and ten random UCSP instances. The experimental results confirmed its effectiveness. Besides, the in-depth analysis confirmed each component's effectiveness for solving UCSP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.209-220
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• 2014

Compressive Sensing (CS) is a new signal acquisition paradigm which enables sampling under Nyquist rate for a special kind of signal called sparse signal. There are plenty of CS recovery methods but their performance are still challenging, especially at a low sub-rate. For CS recovery of natural images, regularizations exploiting some prior information can be used in order to enhance CS performance. In this context, this paper addresses improving quality of reconstructed natural images based on Dantzig selector and smooth filters (i.e., Gaussian filter and nonlocal means filter) to generate a new regularization called smooth residual error regularization. Moreover, total variation has been proved for its success in preserving edge objects and boundary of reconstructed images. Therefore, effectiveness of the proposed regularization is verified by experimenting it using augmented Lagrangian total variation minimization. This framework is considered as a new CS recovery seeking smoothness in residual images. Experimental results demonstrate significant improvement of the proposed framework over some other CS recoveries both in subjective and objective qualities. In the best case, our algorithm gains up to 9.14 dB compared with the CS recovery using Bayesian framework.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• The Journal of Korean Academy of Prosthodontics
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• v.19 no.1
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• pp.7-16
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• 1981

The technology of precision attachments has developed at such a pace that from a very few T-shaped attachments and bar attachments from the years 1915 to 1935 since removable bridge utilizing a T-shaped intracoronal attachment was constructed by Dr. Herman E.S. Chayes in 1906. There are now more than 120 models of the most diversified designs, ready made or laboratory fashioned. In 1971, 126 attachments were listed and classified by Mensor in his E M Attachment Selector. This selector consists of five charts giving specifications as to type, vertical dimensions, application, type of resilience, size of movement, type of retention and type of material and alloy. Thus the E M Attachment Selector is a useful guide for dentists to choose the attachment for his patients. But dentists should apply the attachment in each patient's case according to an accurate diagnosis and treatment plan. This paper is a case report of removable partial dentures utilizing CSP, PD and Bar attachment on a patient who needed full mouth reconstruction. Patient has right first, second molar and left first molar on the upper arch and also left first molar, first premolar and right canine on the lower arch. (Fig. 5)All remaining teeth are relatively healthy in their supporting tissues. On upper arch, ring shape CSP attachment was designed on left first molar and modified ring shape CSP attachment was designed on right first and second molar as the direct retainer of the removable partial denture. Full palatal coverage was used as the major connector in this case. (Fig. 23) On lower arch, author first splinted with a fixed bridge between left first molar and second premolar and a splint bar between left second premolar and right canine. (Fig. 11) A lower removable partial denture in which was designed with an Aker clasp on the left first molar and a PD attachment on .the right canine was constructed. (Fig. 17) This denture could get additional support from anterior splint bar. After both removable partial dentures were delivered to the patient (Fig. 26), author evaluated function of the dentures and supporting structures of the abutment teeth by means of clinical and X-ray examinations for eighteen months. According to the examination data author came to the conclusion that the prognosis of this case was excellent.

• KIPS Transactions on Computer and Communication Systems
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• v.1 no.1
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• pp.1-10
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• 2012

The way-lookup cache and the way-tracking cache are considered to be the most energy-efficient when used for level 1 and level 2 caches, respectively. This paper proposes an energy-efficient set-associative cache using the bi-mode way-selector that combines the way selecting techniques of the way-tracking cache and the way-lookup cache. The simulation results using an Alpha 21264-based system show that the bi-mode way-selecting L1 instruction cache consumes 27.57% of the energy consumed by the conventional set-associative cache and that it is as energy-efficient as the way-lookup cache when used for L1 instruction cache. The bi-mode way-selecting L1 data cache consumes 28.42% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-lookup cache by 15.54% when used for L1 data cache. The bi-mode way-selecting L2 cache consumes 15.41% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-tracking cache by 16.16% when used for unified L2 cache. These results show that the proposed cache can provide the best level of energy-efficiency regardless of the cache level.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.697-700
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• 2000

This paper introduces a new rotor position estimation algorithm for the SRM based on the magnetizing curves of aligned and unaligned rotor positions. The flux linkage is calculated by the measured data from phase voltage and phase current and the calculated data are used as the input of magnetizing profiles for rotor position detection. Each of the magnetizing profiles consisted of the methods using the neural network and fuzzy algorithm And also the optima phase is selected by phase selector. To demonstrate the promise of this approach the proposed rotor position estimation algorithms are verified by the experiment results or variable spee range.

• Journal of the Korean Statistical Society
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• v.30 no.1
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• pp.21-30
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• 2001

Suppose we observe a set of data (X$_1$,Y$_1$(, …, (X$_{n}$,Y$_{n}$) and use the Nadaraya-Watson regression estimator to estimate m(x)=E(Y│X=x). in this article bandwidth selection problem for the Nadaraya-Watson regression estimator is investigated. In particular cross validation method based on average square error(ASE) is considered. Theoretical results here include a central limit theorem that quantifies convergence rates of the bandwidth selector.tor.

• IE interfaces
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• v.17 no.4
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• pp.466-471
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• 2004

In this paper, I develop a simple dynamic resource allocation algorithm that reduces the call blocking rate by improving the resource utilization of the WCDMA (Wideband Code Division Multiple Access) systems under multimedia service environment. Simulation results show that the proposed algorithm significantly reduces the blocking rate of high speed multimedia calls. The algorithm developed in this paper is currently working in the commercial WCDMA IMT-2000 system.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.179-183
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• 1999

This paper describes a new method for indirect sensing of the rotor position in switched reluctance motors using fuzzy logic algorithm. Through a novel fuzzy algorithm, the complete SRM magnetizing characterization is first constructed, and then used to estimate the rotor position. And also, the optimized phase is selected by phase selector. To demonstrate the promise of this approach, the proposed rotor position estimation algorithm is simulated for variable speed range.