• Title/Summary/Keyword: Selection circuit

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The dynamic production scheduling on flexible flowshop systems using simulation (유연흐름 생산시스템에서의 시뮬레이션을 이용한 동적일정계획 연구)

  • 우훈식
    • Journal of the Korea Society for Simulation
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    • v.5 no.2
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    • pp.1-12
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    • 1996
  • Utilizing the simulation approaches, the dynamic production scheduling system FOLS(Flexible flowshop On-Line Simulation) is developed under the flexible flowshop environment. When an interruption such as machine failure/recovery is occurred at the shop floor, the FOLS system performs evaluations for job selection rule oriented alternatives, and generates a dynamic production schedule based on the collected current shop floor data. For the case study, the FOLS system is applied to the printed circuit card assembly(PCCA) line and simulation results are reported.

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Switching Angle Selection for Maximum Torque in Toroidal SRM (Toroidal SRM의 최대토크 스위칭각 선정)

  • 차현록;김현덕;김광헌;임영철;최유영;최강식;전흥기
    • Proceedings of the KIPE Conference
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    • 1999.07a
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    • pp.135-138
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    • 1999
  • This paper analysis magnetic circuit of toroida SRM and simulate optimal switching angle. In this troidal SRM, two of three phase are energized at an arbitrary instance while it is with only one phase in case of typical SRM. It has many advantages in the size of machine and power efficiency. Not only typically Known topologies witched reluctance motors such as asymmetric converter but full bridge converter are safe to employ

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A Zero-voltage-transition PFC Circuit Based on IC UC3855

  • Shi, Lisheng;Chen, Limin;Chen, Baojiang
    • Proceedings of the KIPE Conference
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    • 1998.10a
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    • pp.50-55
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    • 1998
  • This paper introduces the advantages of zero voltage transition(ZVT) boost converter for power factor correction and analyzes the control method of ZVT with IC UC3855. Practical design issues which include the components selection and design procedure are discussed. The experimental results are given.

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A Circuit design with Yield Maximization (Yield 최대화를 고려한 회로설계)

  • 김희석;임재석
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.22 no.5
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    • pp.102-109
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    • 1985
  • A new yield maximization procedure by investigating method of the multidimensional Monte Carlo integration is presented. And then maximum yield is obtained by the new modified weight selection algorithm applied to objective function of MOSFET NAND GATE Also this yield maximization procedure can be applied to nonconvex objective function.

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Problems and Control Measures of Industrial Cooling Water (공업용 냉각수의 문제점과 처리법)

  • Bae, Jong-Su;Lee, Gyu-Hwa
    • 한국기계연구소 소보
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    • s.16
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    • pp.117-126
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    • 1986
  • Trouble-free operation of cooling water systems is essential for efficient pro¬duction in most industrial facilities. Improper water treatments frequently cause such problems as corrosion, scaling, fouling and slime formation. Water quality, methods of cooling and materials of construction in the cooling circuit should be carefully studied before making selection of the water treatment programs. This paper reviewed cooling water problems encountered frequently in the open recirculating cooling systems and discussed the counter measures how to cope with them.

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Design Property Proof of Traction Motor for Urban Transit EMU by FEM Analysis (도시철도차량 표준전동차용 견인전동기의 유한요소 해석에 의한 설계특성 검증)

  • Lee, S.G.;Wang, J.B.;Kim, M.Y.;Park, H.J.
    • Proceedings of the KIEE Conference
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    • 1999.07a
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    • pp.458-460
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    • 1999
  • In this paper, the results of FEM electromagnetic analysis performed in the standardization development of traction motor for EMU are reviewed. The selection of optimal design parameter and performance analysis are proven through the complement of the circuit parameters on the basis of Performance test for developed traction motor.

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Pressure Control Characteristics of a 2-Way Solenoid Valve Driven by PWM Signal (2방향 전자밸브의 PWM 신호에 의한 압력제어 특성)

  • Jeong, Heon-Sul;Kim, Hyoung-Eui
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.26 no.8
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    • pp.1565-1576
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    • 2002
  • By way of driving a 2-way on/off solenoid hydraulic valve with a pulse width modulation (PWM) signal, control of the pressure in a certain volume is frequently used in various applications. However, the pressure built-up according to the duty ratio and carrier frequency of the PWM signal is not so well understood. In order to clarify the characteristics of 2-way valve hydraulic pressure control systems, in this paper two formula fur the mean and ripple of the load pressure were derived through theoretical analysis. And the accuracy of the derived formula were verified by comparison with the experimental test result. Generally 2-way valve systems are constructed as a bleed-off circuit, while 3-way valves are used as a control element in a meter-in circuit pressure control system. In a bleed-off circuit, the system supply pressure from a hydraulic power pack does not remain constant, but changes according to their external load. In turn, the relief valve in the hydraulic power pack reacts accordingly showing complicated dynamic behavior, which makes an analytical study difficult. In order to resolve the problem, simple but accurate empirical dynamic models fer a bleed-off system were used in the course of formula derivation. As the result, selection criteria for two major control parameters of the driving signal is established and the basic strategy to suppress the unnecessary pressure fluctuation can be provided for a hydraulic pressure control system using a 2-way on/off solenoid valve.

VLSI Design of EPR-4 Viterbi Decoder for Magnetic Disk Read Channel (자기 디스크 출력 채널용 EPR-4 비터비 디코더의 VLSI 설계)

  • ;Bang-Sup Song
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7A
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    • pp.1090-1098
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    • 1999
  • In this paper ERP-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2's complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.3 volts.

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Design of New Built-ln Current Sensor for On-Line Testing (On-line 테스팅을 위한 새로운 내장형 전류 감지 회로의 설계)

  • Gwak, Cheol-Ho;Kim, Jeong-Beom
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.7
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    • pp.493-502
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    • 2001
  • This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

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A CMOS Analog Front End for a WPAN Zero-IF Receiver

  • Moon, Yeon-Kug;Seo, Hae-Moon;Park, Yong-Kuk;Won, Kwang-Ho;Lim, Seung-Ok;Kang, Jeong-Hoon;Park, Young-Choong;Yoon, Myung-Hyun;Yoo, June-Jae;Kim, Seong-Dong
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.769-772
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    • 2005
  • This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

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