• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.13-26
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• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2980-2988
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• 1998

This paper describes the design of asynchronous adders based on carry selection and carry bypass techniques. The designs are faster than existing asynchronous adders which are based on ripple carry technique. It is caused by reducing the carry transfer time by using carry selection and carry bypass techniques. Also, the design uses tree structure to reduce the completion sensing time. The proposed adders are designed with CMOS domino logic and experimented with HSPICE simulator. Experimental results show that the proposed adders can be faster about 50% in average cases than previous ripple carry adders.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• Journal of Electrical Engineering and Technology
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• v.8 no.1
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• pp.168-175
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• 2013

This paper presents compact dual-band WLAN filter and filter module. They were developed by embedding all of the passive lumped elements into a LTCC substrate. In order to reduce the size/volume of the filter and avoid EM parasitic couplings between the passive elements, the proposed filter was designed using a 3rd order Chebyshev circuit topology and J-inverter transformation technology. The 3rd order Chebyshev bandpass filter was firstly designed for the band-selection of the 802.11b and was then transformed using finite transmission zeros technologies. Finally, the dual-band filter was realized by adding two notch resonators to the 802.11b filter circuit for the band-selection of the 802.11a/g. The maximum insertion losses in the lower and higher passbands were better than 2.0 and 1.3 dB with minimum return losses of 15 and 14 dB, respectively. Furthermore, the filter was integrated with a diplexer to clearly split the signals between 2 and 5 GHz. The maximum insertion and minimum return losses of the fabricated module were 2.2 and 14 dB at 2.4 - 2.5 GHz, and 1.6 and 19 dB at 5.15 - 5.85 GHz, respectively. The overall volume of the fabricated filter was $2.7{\times}2.3{\times}0.59mm^3$.

• Annals of Clinical Neurophysiology
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• v.8 no.2
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• pp.107-124
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• 2006

The basal ganglia are a group of nuclei located in the deep portion of the brain. Along with the cerebellum, the basal ganglia have a major role in controlling human voluntary movements, and their dysfunction is apparently responsible for various involuntary movements. Although the exact mechanism of how the basal ganglia control movements has yet to be clarified, the model of focused selection (through the direct pathway) and tonic inhibition (via the indirect pathway) is proposed to be a principal functional model of the basal ganglia. Parkinson's disease (PD) is classically characterized by bradykinesia, rigidity and tremor-at-rest. All features seem to be associated with dopamine depletion resulting from the degeneration of the nigrostriatal pathway, which produces reduced activity of the direct pathway and a concurrent enhancement of excitatory output from STN. This change may result in increased tonic background inhibition and reduced focused selection via the direct pathway, causing difficulties in performing voluntary movements selectively. However, it has not been possible to define a single underlying pathophysiologic mechanism that explains all parkinsonian symptoms. Here the data that give separate understanding to each of the three classic features are discussed.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.42-48
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• 2016

Light-emitting diode (LED) drivers are recently replacing fluorescent lamps; these drivers can operate adaptively with various ballasts without modifying and removing such ballasts. To satisfy these trends, a LED driver that is compatible with both electronic and magnetic ballasts is proposed in this study. Unlike conventional LED drivers, the proposed driver has a ballast recognition circuit and a mode selection circuit to operate ballasts at optimal conditions. Therefore, it features low voltage stress, high efficiency, and good compatibility with both electronic and magnetic ballasts. Moreover, it can be compatible with a wide selection of ballasts from various manufacturers. To confirm the validity of the proposed LED driver, results of the theoretical analysis and experimental verification performed on a 15 W-rated prototype are presented.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.2
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• pp.5-13
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• 1976

An analytical and experimental design procedure is described for the Capacitor Discharge Ignition (CDI) System with a view to fuel saving ann reduction of gas exhaustion and maintenance need. Specifically, the input and output voltage and current of a given ignition coil were calculated by using a simplified circuit model for the discharging system. The results were compared with the experimental results, from which ratings of the charging capacitor, the SCR and the diodes and the required output valtage of the DC.DC converter were determined so as to satisfy the optimum ignition conditions. Protection circuits for excessive dv/dt and di/dt for the SCR were also analyzed and the results were compared with the observed results, which facilitate selection of the SCR and design of the protection circuit and the trigger circuit. Also, design of the DC.DC converter was simplified based on the analysis and experimental results of the behavior of the converter, An experimental, yet practical CDI system was built, which showed satisfactory performance in the laboratory and field tests. The results were also reported.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.3
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• pp.174-181
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• 2018

This study introduces a systematic approach to selecting the internal parameters applied to the equivalent electrical-circuit model (EECM) of a lithium titanium oxide ($Li_4Ti_5O_{12}$; LTO) rechargeable cell. Based on the dynamic characteristic of the cell, a simplified EECM consisting of an open-circuit voltage (OCV), an ohmic resistance, and an RC ladder is fabricated. To select the internal parameters of a simplified EECM, experiments on discharge capacity, OCV, and discharge/charge resistances are performed using hybrid pulse power characterization and direct current internal resistance (DCIR) measurements over the full state-of-charge (SOC) range. The experimental results of the LTO rechargeable cell highlight the importance of correct selection of internal parameters that can reduce EECM errors. This study clearly provides experimental procedures, internal parameters results, and EECM guidelines for adaptive control-based SOC estimation for LTO rechargeable cells.

• Korean Journal of Materials Research
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• v.30 no.7
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• pp.327-332
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• 2020

Laser induced surface activation (LISA) technology requires refined selection of process variables to fabricate conductive microcircuits on a general polymer material. Among the process variables, laser mode is one of the crucial factors to make a reliable conductor pattern. Here we compare the continuous wave (CW) laser mode with the pulse wave (PW) laser mode through determination of the surface roughness and circuit accuracy. In the CW laser mode, the surface roughness is pronounced during the implementation of the conductive circuit, which results in uneven plating. In the PW laser mode, the surface is relatively smooth and uniform, and the formed conductive circuit layer has few defects with excellent adhesion to the polymer material. As a result of a change of laser mode from CW to PW, the value of Ra of the polymer material decreases from 0.6 ㎛ to 0.2 ㎛; the value of Ra after the plating process decreases from 0.8 ㎛ to 0.4 ㎛, and a tight bonding force between the polymer source material and the conductive copper plating layer is achieved. In conclusion, this study shows that the PW laser process yields an excellent conductive circuit on a polymeric material.