• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.88-99
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• 1992

This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.

• Journal of The Korean Astronomical Society
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• v.10 no.1
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• pp.31-38
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• 1977

To reduce the instrumental and calibration errors in the photoelectric photometry as much as possible it is necessary to select the optimum photocell voltage and energy attenaution and to observe as many standard stars as possible over the wide range of color, spectral type and air mass.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.633-634
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• 2007

• Journal of the korean veterinary medical association
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• v.18 no.3
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• pp.10-19
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• 1982

The present conditions of at rophic rhinitis of swine or Bordetellosis of swine and recent research ,progress have been introduced. Phase variations are emphasized to select a strain as an antigen for serolo diagnosis and an effective protective substance

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1996.10a
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• pp.257-260
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• 1996

This study is about the construction of algorithm for selecting Yongshin of the Four Pillars. To emulate the method the expert uses when he select the Yongshin, we introduce the Hopfield Network. The result of the simulation classified with Yongshin is presented.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.598-599
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• 2017

In motor application, High efficiency is important. So Design engineer select small gate resistor for lower switching. But There is side effect with small gate resistor. It makes large dv/dt and system request large EMI filter. It makes price increase. This paper introduce about gate drive IC which have solution both of lower loss and EMI issue.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.10a
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• pp.553-554
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• 2013

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.969-973
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• 1995

In this paper, a new parallel Multiplier array is proposed to reduce the multiplication time by modifying CAS(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA (doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.93-99
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• 2004

At present, LG Electronics pushes ahead to eliminate the Pb(Lead) -a hazardous material- from all products. Especially, we have performed to select the optimum standard composition of lead free alloy for the application to products for about 3 years from 2000. These days, we have the chance for applying to the mass-production. This project constructed the system for applying the lead free solders on consumer electronic products, which is one of the major products of the LG Electronics. To select the lead free solders with corresponding to the product features, we have passed through the test and applied with Sn-3.0Ag-0.5Cu alloy system to our products, and for the application to the high melting temperature composition, we secured the thermal resistance of the many parts and substrate and optimized the processing conditions. We have operated the temperature cycling test and the high temperature storage test under the standards to confirm the reliability of the products. On these samples, we considered the consequence of our decision by the operating test. For the long life time of the product, we have operated the temperature cycling test at $-45^{\circ}C-+125^{\circ}C$, 1 cycle/hour, 1000 cycles. Also we have tested the tin whisker growth about lead free plating on lead finish. We have analyzed with the SEM, EDS and any other equipment for confirming the failure mode at the joint and the tin whisker growth on lead free finish.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.1025-1032
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• 1998

In this paper, the PLD design tool which realizes a digital circuit as PLD, by using EDIF netlist of the digital circuit designed at OrCAD have been developed. This paper is proposed the following algorithms: JIE(Joined Information Extractor) which extracts the connecting information between both cells in order to realize the digital circuit as PLD using the EDIF netlist, FND(Feedback Node Detector) which look into whether feedback exists or not, BEG(Boolean Equation Generator) which generates a boolean equation, and so on. Also, this paper is developed auto-select function which selects the PLD element with consideration of number of I/O variables of the minimized boolean equation, and algorithm generation JEDEC file of GAL6001 and GAL6002, having a forms of EPLD which is bigger than PLD.