• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.280-284
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• 2005

In ubiquitous computing environment, An RFID system will be the important way that recognizing an object instead of Bar-code system. But a privacy infringement problem is predicted between a tag and leader to be serious. There is many difficulty that just uses an existing research method because it has an Hardware restriction. Therefore we will suggest that A RFID Privacy Protect system using Hareware friendly security algorithm. we will use RC5 and CBC_MAC because the tag has hardware restriction .To implement, We will simulate and test on One chip microprcessor environment. In the result of the experiment, We will know that a suggested system solves privacy problem on RFID system that it was using CBC-MAC and RC5 security algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.6
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• pp.59-65
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• 2010

Since an attacker can occur an error in cryptographic device during encryption process and extract secret key, the fault injection attack has become a serious threat in chip security. In this paper, we show that an attacker can retrieve the 128-bits secret key using fault injection attack on the for statement of final round key addition in AES implementation. To verify possibility of our proposal, we implement the AES system on ATmega128 microcontroller and try to inject a fault using laser beam. As a result, we can extract 128-bits secret key through just one success of fault injection.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.55-60
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• 2017

This paper is proposed on the transmit Method Finger-Printer Scanning of Mutual Capacitance Touch Screen Panel Using Differential Pulse for improving the security of computer information. This system is composed of differential pulse generator and Ring-Counter, also Supply voltage is 5V. this system generates the Pulse wave which is composed of In-Phase and Out of Phase at 1MHz while period of 2m/s. it is designed and be able to operate four channels. overall power consumption is approximately 78.08nW. This prototype is implemented in 0.25um CMOS Process and Chip area is $870um{\times}880um$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.97-107
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• 2004

This paper presents an System-on-Chip(SoC) implementation of fingerprint feature extraction system. Typical fingerprint feature extraction systems employ binarization and thinning processes which cause many extraction errors for low qualify fingerprint images and degrade the accuracy of the entire fingerprint recognition system. To solve these problems, an algorithm directly following ridgelines without the binarization and thinning process has been proposed. However, the computational requirement of the algorithm makes it hard to implement it on SoCs by using software only. This paper presents an implementation of the ridge-following algorithm onto SoCs. The algorithm has been modified to increase the efficiency of hardwares. Each function block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The fingerprint feature extraction system has been developed as an IP for SoCs, hence it can be used on many kinds of SoCs for smart cards.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.59-68
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• 2006

Although the cryptographic algorithms in IC chip such as smart card are secure against mathematical analysis attack, they are susceptible to side channel attacks in real implementation. In this paper, we analyze the security of smart card using a developed experimental tool which can perform power analysis attacks and fault insertion attacks. As a result, raw smart card implemented SEED and ARIA without any countermeasure is vulnerable against differential power analysis(DPA) attack. However, in fault attack about voltage and clock on RSA with CRT, the card is secure due to its physical countermeasures.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.5
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• pp.891-898
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• 2022

Along with global interest, drones are expanding the base of utilization such as transportation of goods, forest protection, and safety management, and cluster flights are being applied in various fields such as military operations and environmental monitoring. Currently, specialized networks such as e-UM 5G for services in specific industries are being established in Korea. In this regard, drone systems are also moving to establish specialized networks to provide services that are fused with AI and autonomous flight. As drones converge with various services, various security threats in various environments are also subordinated, and in response, requirements and guidelines for drone security are being prepared in Korea. In this paper, we propose a technology method for peer identification and safe information provision between cluster flight drones by utilizing a cryptographic module equipped with wireless LAN and quantum entropy-based random number generator in a cluster flight system and a mobile communication network such as e-UM 5G.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.157-162
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• 2010

Due to the IT development, RFID/USN became very familiar means of communication. However, because of increased number, security, and size constraints of nodes, it is insufficient to implement a variety of services. To solve these problems, this paper suggests RI-RSA, which is an appropriate asymmetric cryptographic system for RFID/USN environment. The proposed RI-RSA cryptographic system is easy to implement. To increase the processing speed, RI-RSA was suggested by subdividing the multiplication section into two-dimensional, where bottleneck phenomena occurs, and it was implemented in the hardware chip level. The simulation result verified that it caused 6% of circuit reduction, and for the processing speed, RI-RSA was 30% faster compare to the existing RSA.

• ETRI Journal
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• v.33 no.4
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• Convergence Security Journal
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• v.13 no.4
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• pp.27-32
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• 2013

In this paper, technologies applied to design urination detection device on diaper that issues an alarm signal to guardian within 10~20m are introduced. It features power saving that uses both low power bluetooth v4.0 chip and low-power program scheme that makes sensor and mirco-controller to be sleep mode while data is not receiving from sensor. Urination detection algorithm that utilizes the difference between previous sensing data and current values is used to improve the degree of the detection precision level. The device designed with the suggested technologies shows the performance that is 100ml of the minimum urine amount for detection, more than 90% of urination detection degree, and 100% of wireless communication success rate.