• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.573-575
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• 1998

실시간 내장형 시스템(real-time embedded system)의 반응 동작(reactive behavior)을 정확하게 분석하기 위해서 상태차트(statechart)에 바탕을 둔 객체 지향 모델링 방법론들이 많이 사용되고 있다. 하지만 이들 방법론들은 경성 실시간 시스템(hard real-time system)이라면 반드시 고려해야할 스케줄링 가능성분석(scheduability analysis)에 필요한 시간에 대한 정보와 시간 제약을 정확히 나타내지 못하는 문제점이 있다. 본 논문에서는 최근 OMG(Object Management Group)에서 객체 지향개발의 기준으로 채택된 UML(Unifies Modeling Language) ver1.1을 사용하여 실시간 내장형 시스템의 반응 동작과 시스템의 시제 동작(temporal behavior)을 모델링하여, 모델링된 시스템이 스케줄링 가능성 분석이 효과적으로 이루어지는 방안을 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.294-299
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• 1999

CCSR은 CCS에 시간적인 개념이 추가된 실시간 명세 언어로 실시간 프로세스의 정적 분석에 이용되고 있다. CCSR은 프로세스 전이 규칙을 이용하여 프로세스 동작의 관심 부분만 하여 분석하기 때문에 전체 태스크(task)의 동작을 분석하는데 적용하기 어렵고, 전이규칙에 따른 상태 변화를 이해하기 어렵다. E-TCPN은 시간 요소가 첨가된 Petri Net의 변형된 형태로 실시간 시스템의 분석과 모델링을 위한 형식적(formal) 방법을 제공한다. 본 논문에서는 CCSR로 표현된 프로세스 동작을 E-TCPN 모델에 적용함으로써 실시간 시스템을 중요한 사건을 중심으로 전체 태스크의 동작 과정을 표현하고 프로세스의 수행 과정을 이해하기 쉽도록 CCSR을 변형하여, E-TCPN 명세 모델에 적용하고, 적용된 E-TCPN으로 스케줄링가능성 분석 알고리즘을 제안하고 구현하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1753-1756
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• 2010

최근 들어 가상화 기술은 서버의 통합에 뿐만 아니라, 임베디드 시스템에서도 널리 사용되고 있다. 하지만, 가상화 시스템에서는 물리 프로세서가 게스트 운영체제에게 직접 전달되지 않으며, 게스트 운영체제는 가상 프로세서를 통해서 실행할 수 밖에 없다. 따라서, 기존의 처리량 기준의 공평성 스케줄러가 가상머신 모니터에서 동작하는 경우, 실시간 스케줄링이 불가능하다. 본 연구에서는 멀티코어 기반의 가상화 시스템에서 실시간 태스크의 실행을 보장하는 기법을 소개한다. 특히, 본 논문에서는 계층형 스케줄링의 특성과 최대 병렬성 조건을 통하여 멀티코어 가상머신의 스케줄 가능성 분석 기법을 제시한다.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.5
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• pp.91-101
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• 2014

In this study, we presented a timing verification method for a passenger car diesel engine management system (EMS) using measurement-based worst-case execution time (WCET) analysis. In order to cope with AUTOSAR-compliant software architecture, a development process model is proposed. In the process model, a runnable is regarded as a test unit and its temporal behavior (i.e. maximum observed execution time, MOET) is obtained along with on-target functionality evaluation results during online unit test. Furthermore, a cost-effective framework for online unit test is proposed. Because the runtime environment layer and the standard calibration environment are utilized to implement test interface, additional resource consumption of the target processor is minimized. Using the proposed development process model and unit test framework, the MOETs of 86 runnables for diesel EMS are obtained with 213 unit test cases. Using the obtained MOETs of runnables, the WCETs of tasks are estimated and the schedulability is evaluated. From the schedulability analysis results, the problems of the initially designed schedule table is recognized and it is fixed by redesigning of the runnable mapping and task offset. Through the various test scenarios, the proposed method is validated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2277-2282
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• 2010

O(1) time synthetic utilization is not considered periodic tasks, except scheduling methods for aperiodic tasks where one of the aperiodic tasks is a scheduling method. But really aperiodic tasks scheduling method is composed of mixed task types. Aperiodic task scheduling method guarantee an analysis of the schedualibility of aperiodic task. The set of mixed tasks periodic and aperiodic tasks scheduling method uses synthetic utilization that is presented in this paper. The new method shows that schedulability increases 20% aperiodic server method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.351-356
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• 2015

Synthetic utilization on multiprocessor system is not considered periodic tasks, except scheduling methods for aperiodic tasks where one of the real-time aperiodic tasks is a scheduling method. But really aperiodic tasks scheduling method is composed of mixed task types. Aperiodic task scheduling method guarantee an analysis of the schedualibility of aperiodic task. The set of mixed tasks periodic and aperiodic tasks scheduling method uses improved synthetic utilization that is presented in this paper. The new method shows that schedulability increases aperiodic server method.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1418-1432
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• 1996

In addition t improved availability, replication of data can enhance performance of distributed real-time transaction processing system by allowing transactions initiated at multiple node to be processed concurrently. To satisfy both the consistency and real-time constraints, it is necessary to integrate concurrency control and atomic commitment protocols with time-driven scheduling methods. blocking caused by existing concurrency control protocols is incompatible with time-driven scheduling because they cannot schedule transactions to meet given deadlines. To maintain consistency of replicated data and to provide a high degree of schedulability and predictability , the proposed time-driven scheduling methods integrate optimistic concurrency control protocols that minimize the duration of blocking and produce the serialization by reflecting the priority transactions. The atomicity of transactions is maintained to ensure successful commitment in distributed environment. Specific time-driven scheduling techniqueare discussed, together with an analysis of the performance of this scheduling.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.337-347
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• 2007

An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this Paper, we address a HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications. From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0% and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.