• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.180-188
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• 1999

${\mu}$-synthesis is applied to design a robust controller for a seeker scan loop system which has model uncertainty and is subject to a external disturbance due to abrupt missile maneuver. The issue of modelling a real-valued parametric uncertainty of a physical seeker scan loop system is discussed. The two-degree-of-frame control structure is employed to obtain better performance. It is shown that ${\mu}$-synthesis provides a superior framework for the robust control design of a seeker scan loop system which exhibits robust performance. The proposed robust control system satisfies design requirements, and especially shows good scanning performances for conical and rosette scan patterns despite parametric uncertainty in real system model.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.3
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• pp.504-514
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• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• Journal of the Korean Society for Precision Engineering
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• v.11 no.2
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• pp.110-119
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• 1994

The Robust Controller for scan-loop is designed using LQG/LTR Methodology. The design and analysis of spiral, rosette and conical scan patterns are discussed. The perfermance and robustness of the LQG/LTR controller are analyzed through experiments and cpmpared with those of the P-controller. Especially to improve the scan performance at large look angle, the cage coil output is linearized using a binomial equation. It is demonstrated that the scan-loop system by the LQG/LTR control is very robust to phase uncertainties.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1191-1195
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• 2009

We present the efficient test wrapper design methodology considering the layout distance of scan chain. To test the scan chains in SoC, the scan chains must be assigned to external TAM(Test Access Mechanism) lines. The scan chains in IP were placed and routed without any timing violation at normal mode. However, in test mode, the scan chains have the additional layout distance after TAM line assignment, which can cause the timing violation of flip-flops in scan chains. This paper proposes a new test wrapper design considering layout distance of scan chains with timing violation free.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.749-758
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• 1995

There are many testable design techniques, among which Scan path and BIST techniques are mainly used. In this paper, the increase of design effectiveness is discussed, when these techniques are applied to the practical implementation of chips. The following techniques are presented : 1) Blocks are commonly used to reduce test time without hardware increase, 2) MUX is used to implement the shortest Scan path, 3) Scan register is used which controls and/or observes several blocks to avoid the increase of hardware.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1177-1184
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• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• The Journal of Advanced Prosthodontics
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• v.12 no.3
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• pp.107-113
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• 2020

PURPOSE. The aim of this study was to examine the importance of the defect-free scanning of a scan body by assessing the accuracy of virtual implant positioning in computer-aided design (CAD) software when the scan body image is improperly scanned. MATERIALS AND METHODS. A scan body was digitized in a dentiform model using an intraoral scanner, and scanned images with differing levels of image deficiency were generated: 5%, 10%, and 15% deficiency in the flat or rounded area. Using a best-fit image matching algorithm on each of the deficient scan body images, corresponding virtual implants were created. The accuracy of the implant position was evaluated by comparing the linear and angular discrepancies between the actual and virtual positions of the implant. Kruskal-Wallis tests and Mann-Whitney U tests with Bonferroni correction were used to determine the statistical differences among the seven scanned image deficiency groups (α=.05). RESULTS. In general, the linear and angular discrepancies of the implant position in the software increased as the deficiency of the scan body images increased. A 15% scan body image deficiency generated larger discrepancies than deficiency of 5% and 10%. The difference of scan defect position, flat or rounded area, did not affect the accuracy of virtual implant orientation at 5% and 10% deficiency level, but did affect the accuracy at 15% deficiency level. CONCLUSION. Deficiencies in the scanned images of a scan body can decrease the accuracy of the implant positioning in CAD software when the defect is large, thus leading to the incorrect fabrication of implant prostheses.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.33-39
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• 2009

This paper presents a new secure scan design technique to protect secret key from scan-based side channel attack for an Advanced Encryption Standard(AES) core embedded on an System-on-a-Chip(SoC). Our proposed secure scan design technique can be applied to crypto IF core which is optimized for applications without the IP core modification. The IEEE1149.1 standard is kept, and low area and power consumption overheads and high fault coverage can be achieved compared to the existing methods.