• Journal of the Korean Society for Precision Engineering
• /
• v.31 no.9
• /
• pp.813-820
• /
• 2014

This paper presents design and performance validation of a method for motion compensation using fast steering mirror. First of all, the schematics of the Electro Optical/Infra-Red (EO/IR) and step-stare image gathering system for an aerial reconnaissance are introduced. Because of the steering mirror with low inertia so called Back scan mechanism (BSM), the fast step-stare image gathering technique that is required for taking a high-definition still image will be realized. After then, the BSM hardware includes motors and feedback sensors are introduced. Also, the motion profile for BSM will be designed to compensate roll scan motion of the gimbals. At the end of this paper, designed profile and tracking performance of the EO/IR system with BSM will be validated through experiments.

• Journal of the Optical Society of Korea
• /
• v.9 no.1
• /
• pp.26-31
• /
• 2005

We describe the design and the implementation of video-rate reflection confocal scanning microscopy (CSM) using an acousto-optical deflector (AOD) for the fast horizontal scan and a galvanometer mirror (GM) for the slow vertical scan. Design parameters of the optical system are determined for optimal resolution and contrast. The OSLO simulations show that the performances of CSM are not changed with deflection angle and the wavefront errors of the system are less than 0.012λ. To evaluate the performances of designed CSM, we do a series of tests, measuring lateral and axial resolution, real time image acquisition. Due to a higher axial resolution compared with conventional microscopy, CSM can detect the surface of sub-micrometer features. We detect 138㎚ line shape pattern with a video-rate (30 frm/sec). And 10㎚ axial resolution is archived. The lateral resolution of the topographic images will be further enhanced by differential confocal microscopy (DCM) method and computational algorithms.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.7
• /
• pp.86-94
• /
• 1998

The rosette-scan seeker is a device mounted on the infrared guided missile. It offers the positions and iamges of target to missiles servo system by scanning a space about target in rosette pattern with a single detector. An instantaneous field of view (IFOV), which is a diameter of a detector moving along the path of the rosette pattern, has the property that its smaller size provide the less interference of background signals and detector noise. If its size is too small to voer the total field of view (TFOV), however, it produces the invisible regions in the TFOV. In this case, the invisible regions cause the performance of the seeker to deteriorate. For full scan-coverage, it is necessary to design the small IFOV without the invisible regions in the TFOV, as possible. In this paper, we propose the new method of designing the smaller IFOV than the conventional method and verify full coverage of the scanned region. By comparing the nose equivalent flux density (NEFD) of the proposed method with the that of the conventional one, we confirm that the former is better than the latter in terms of performance.

• The Transactions of the Korea Information Processing Society
• /
• v.1 no.2
• /
• pp.272-278
• /
• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.30-37
• /
• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• Journal of the Korean Society for Precision Engineering
• /
• v.26 no.8
• /
• pp.29-34
• /
• 2009

• ETRI Journal
• /
• v.25 no.5
• /
• pp.288-296
• /
• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• The Magazine of the IEIE
• /
• v.22 no.12
• /
• pp.93-104
• /
• 1995

디지탈 회로를 구현한 칩 및 보드의 시험 비용을 줄이기 위하여 사용되는 스캔 설계 기술 동향에 대하여 기술하였다. 스캔 설계 기술은 칩 수준에서 먼저 적용되기 시작하였다. 회로의 모든 플립플롭을 스캔할 수 있도록 하는 완전 스캔이 먼저 개발되었고, 최근에는 플립플롭의 일부분만 스캔할 수 있도록 하는 부분 스캔 기술이 활발하게 논의되고 있다. 한편 보드의 시험에 있어서도 보드에 실장되는 칩의 밀도가 증가되고, 표면 실장 기술이 일반화됨에 따라 종래의 시험 기술로는 충분한 시험을 거치는 것이 불가능하게 되었다. 따라서, 칩에 적용되던 기법과 유사한 스캔 설계 기술이 적용되기 시작하였다. 이를 경계 스캔(Boundary Scan)이라고 하는데, 이 기술은 80년대 후반부터 본격적으로 논의되기 시작하였다. 1990년에는 이 기술과 관련된 IEEE의 표준이 제정되어 더욱 많이 적용되는 추세에 있다. 이 논문에서는 이러한 칩 및 보드의 시험을 쉽게하기 위한 스캔 설계 기법의 배경, 발전 과정 및 기술의 내용을 소개한다.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.329-332
• /
• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.2
• /
• pp.94-103
• /
• 1994

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.