• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.6
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• pp.562-567
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• 2000

Many pressure vessels for power and industrial plant are fabricated from low alloy carbon steels. The inner sides of pressure vessels are commonly weld-cladded with austenitic stainless steels to minimize problems of corrosive attack. Disbonding cracks are often detected at the transition region of welding interlayer, which is serious problem to reliability of pressure vessels. We have developed C-scan system to high speed inspection of overlay weld using DSP(digital signal processor). This system consists of signal processing parts (oscilloscope, pulser/receiver, digitizer, DSP), scanner, program and position controller. The developed system has been applied to a practical ultrasonic testing in overlay weld, and demonstrated high speed with precision

• Resources Recycling
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• v.17 no.6
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• pp.43-49
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• 2008

In this study, a scrap sorting system using a color recognition method has been developed to automatically sort out specified materials from a mixture, and its application as been examined in the separation of Cu and other non-ferrous metal parts from a mixture of iron scraps. The system is composed of three parts; measuring, conveying and ejecting parts. The color of scrap surface is recognized by the measuring part consisting of a line-scan camera, light sources and a frame grabber. The recognition is program-controlled by a image processing algorithms, and thus only the scrap part of designated color is separated by the use of air nozzles. In addition, the light system is designed to meet a high speed of sorting process with a frequency-variable inverter and the air nozzled ejectors are to be operated by an I/O interface communication with a hardware controller. In the functional tests of the system, its efficiency in the recognition of Cu scraps from its mixture with Fe ones reaches to more than 90%, and that in the separation more than 80% at a conveying speed of 25 m/min. Therefore, it is expected that the system can be commercialized in the industry of shredder makers if a high efficiency ejecting system is realized.

• Journal of the Korean Society for Nondestructive Testing
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• v.29 no.5
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• pp.493-500
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• 2009

An ultrasonic signal processing algorithm was developed for extracting the information of cracks generated around the keyway of a turbine rotor disk. B-scan images were obtained by using keyway specimens and an ultrasonic scan system with x-y position controller. The B-scan images were used as input images for 2-Dimensional signal processing, and the algorithm was constructed with four processing stages of pre-processing, crack candidate region detection, crack region classification and crack information extraction. It is confirmed by experiments that the developed algorithm is effective for the quantitative evaluation of cracks generated around the keyway of turbine rotor disk.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.51-58
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• 2016

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.85-92
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• 2004

A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.4
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• pp.187-194
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• 2008

This paper proposes an effective countermeasure to an intrinsic hardware vulnerability of the keyboard controller that causes sniffing problem on the password authentication system based on the keyboard input string. Through the vulnerability, some possible attacker is able to snoop whole the password string input from the keyboard even when any of the existing keyboard protection software is running. However, it will be impossible for attackers to gather the exact password strings if the proposed policy is applied to the authentication system though they can sniff the keyboard hardware protocol. It is expected that people can use secure Internet commerce after implementing and applying the proposed policy to the real environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Journal of Sensor Science and Technology
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• v.33 no.4
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• pp.187-195
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• 2024

Light detection and ranging (LiDAR), a widely used sensor in mobile robots and autonomous vehicles, has its most important function as measuring the range of objects in three-dimensional space and generating point clouds. These point clouds consist of the coordinates of each reflection point and can be used for various tasks, such as obstacle detection and environment recognition. However, several processing steps are required, such as three-dimensional modeling, mesh generation, and rendering. Efficient data processing is crucial because LiDAR provides a large number of real-time measurements with high sampling frequencies. Despite the rapid development of controller computational power, simplifying the computational algorithm is still necessary. This paper presents a method for estimating the presence of curbs, humps, and ground tilt using range measurements from a single horizontal or vertical scan instead of point clouds. These features can be obtained by data segmentation based on linearization. The effectiveness of the proposed algorithm was verified by experiments in various environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.895-902
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• 2015

This paper presents a high-speed sensing and noise cancellation technique for large touch screens, which is called FDCS (Frequency Division Concurrent Sensing). Most conventional touch screen detection methods apply excitation pulses sequentially and analyze the sensing signals sequentially, and so are often unacceptably slow for large touch screens. The proposed technique applies sinusoidal signals of orthogonal frequencies simultaneously to all drive lines, and analyzes the signals from each sense line in frequency domain. Its parallel driving allows high speed detection even for a very large touch screens. It enhances the sensing SNR (Signal to Noise Ratio) by introducing a frequency domain noise filtering scheme. We also propose a pre-distortion equalizer, which compensates the drive signals using the inverse transfer function of touch screen panel to further enhance the sensing SNR. Experimental results with a 23" large touch screen show that the proposed technique enhances the frame scan rate by 273% and an SNR by 43dB compared with a conventional scheme.