• Journal of Korea Multimedia Society
• /
• v.6 no.1
• /
• pp.15-27
• /
• 2003

Recently, the volume of data is increasing rapidly in server for multimedia service, according to development of multimedia application environment. In recent research for storage technology the technology like of the SAN(Storage Area Network) advantages in scalibility of storage devices, and can read data from multiple disk arrays through RAID 0, 5. The RAID 0 and 5 translate to logical address to physical address using equation, but in case of adding disks at the system with equation -based mapping, the problem that we must rearrange the whole data in the previous disks happens. We use the mapping table to solve this problem in recent, but we can not load the whole mapping table in main memory because it occupies too large space. Therefore the extra I/Os are demanded to evaluate real physical address of data, so total performance of the system is degraded. In this paper, we propose the mapping method that supports the scalibility in RAID 0 or 5 system. The proposing method applies small metadata, so- called SZIT and simple equation, so it is possible that we make translate logical address to physical address rapidly and it is scalable in disk extending simultaneously Our suggesting method, if we add disks to the striping system for expanding of storage capacity, has an advantage of never stop service. So, SZlT-based mapping method can do online-disk-expanding in real-time service.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.6
• /
• pp.1266-1272
• /
• 1997

Due to the price and performanceof uniprocessor workstations and off-the shelf networking, network of workstations(NOW) ae now a cost-effective parallel processing platform tht is competitive with supercomputers. Meanwhile, current network fiile system protocols rely heavily on a central server to coordinate file activity among client workstations. This central server can become a bottleneck that limits scalibility for environments with large numbers of clients. In this paper, we propsoe a highly reliable and effective software RAID file system on the network of workstation environment. We present results form a trace-driven simulation study that shows that the designed software RAID file system is more effective in the aspect of elapsed time when compared with client/server file systems.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.4
• /
• pp.105-113
• /
• 2008

While the wireless sensor network has a strong point which does not have effect on whole activities of network even though neighboring sensor nods fail activities of some sensor nod or make some functions disappear by the characteristic of similar information detection, it has problems which is slowing down of wireless medium, transfer character with severe error, limited power supply, the impossibility of change by optional arrangement of sensor nods etc. This paper proposes PRML techniques which performs the fittest course searching process to reduce power consumption of entire nods while guarantees the scalability of network organizing sensor nods hierarchically. The proposed technique can scatter the load of cluster head by considering the connectivity with surplus energy of nod and reduce the frequency of communication among the nods. As a result of the analysis in comparison with LEACH-C and HEED technique, PRML technique get efficiency of average 6.4% in energy consuming respect of cluster head, efficiency of average 8% in entire energy consuming respect, and more efficiency of average 7.5% in other energy consuming distribution of network scalability than LEACH-C and HEED technique.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.11
• /
• pp.45-52
• /
• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.