• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.3
• /
• pp.128-133
• /
• 1998

This paper is study on performance analysis of modulator using direct digital frequency synthesizer of Initial Clock Accumulating Method. It has been generally used for PLL or digital frequency synthesizing method to be synthesizd randomly chosen frequency state. In order to improve disadvantage of two methods, we constructed modulator system using DDFS of Initial Clock Accumulating Method. We also confirmed the coherence frequency hopping state and possibility of phase control. The results obtained from the experiments are as follows; First, the synthesized output frequency is proportional to the sampling frequency, according to index, K. Second, the difference of the gain between the basic frequency and the harmonic frequencies was more than 50 [dB], that is, this means facts that is reduced the harmonic frequency factor. Third, coherence frequency hopping state is confirmed by PN code sequence. Here, we confirmed the proposed method cut switching time, this verify facts that is the best characteristic of the frequency hopping. We also verified the fact that the phase varies as the adder is operated set or reset.

• Research in Community and Public Health Nursing
• /
• v.17 no.4
• /
• pp.482-491
• /
• 2006

Purpose: Hemiplegia patients who were attacked by a stroke suffer from hemiplegic disabilities as well as motor disabilities. For them, rehabilitation cure is being carried out broadly. However, it is not enough for them to use the upper extremity than the lower extremity. For the use of the upper extremity, we examined the effect of constraint-induced movement therapy developed in this research on patients who experienced a stroke following hemiplegia. Method: For this study we selected 36 stroke patients who were registered at the community health center through accidental sampling, and assigned 21 of them to the experimental group, and 15 to the control group. The experimental group had constraint-induced movement therapy for 5 days and 7 hours a day from 9 to o'clock in the morning 9 to 4 o'clock in the afternoon 4 including warmup exercise and main exercise in the rehabilitation room, whereas the control group were restricted. Result: As a result of constraint-induced movement therapy, affected side elbow joint flexion range, side shoulder joint extension range and side shoulder joint of the flexion range of motions increased obviously in the experimental group compared to those in the control group. Conclusion: The result above clearly shows that constraint-induced movement therapy is an effective intervention for the rehabilitation of hemiplegia patients in increasing affected side elbow joint of the flexion range of motion, the shoulder joint extension, and the increase of flexion range of motion.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.25-33
• /
• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• Proceedings of the KIEE Conference
• /
• 2008.04a
• /
• pp.59-60
• /
• 2008

In this paper, we investigate the ability of the ARM processor to implement an industrial controller with or without embedded operating system. Discrete-time PID controllers are implemented and tested under various settings e.g. cache on/off, different clock frequencies using S3C2410X chip. A method of real-time application of discrete-time PID controller in WinCE environment is proposed. Based on the test result, we provide the maximum sampling frequencies of PID controller using ARM processor.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.1
• /
• pp.76-81
• /
• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.65-73
• /
• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.11
• /
• pp.61-66
• /
• 2005

This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.48-57
• /
• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of Astronomy and Space Sciences
• /
• v.26 no.2
• /
• pp.229-236
• /
• 2009

KOorea Multi-purpose SATellite(KOMPSAT)-5 will be launched at 550km altitude in 2010. Accurate satellite position(20 cm) and velocity(0.03 cm/s) are required to treat highly precise Synthetic Aperture Radar(SAR) image processing. Ionosphere delay was eliminated using dual frequency GPS data and double differenced GPS measurement removed common clock errors of both GPS satellites and receiver. SAC-C carrier phase data with 0.1 Hz sampling rate was used to achieve precise orbit determination(POD) with ETRI GNSS Precise Orbit Determination(EGPOD) software, which was developed by ETRI. Dynamic model approach was used and satellite's position, velocity, and the coefficients of solar radiation pressure and drag were adjusted once per arc using Batch Least Square Estimator(BLSE) filter. Empirical accelerations for sinusoidal radial, along-track, and cross track terms were also estimated once per revolution for unmodeled dynamics. Additionally piece-wise constant acceleration for cross-track direction was estimated once per arc. The performance of POD was validated by comparing with JPL's Precise Orbit Ephemeris(POE).