• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.101-110
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• 1997

SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2269-2279
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• 1997

SVLIW (Superscalar VLIW) processor, a family of VLIW processors schedules very long instruction words at runtime. If a very long instruction word that is to be issued occurs data dependence relations and/or resource conflicts with those words that were under execution, a long NOP word is issued instead of the word until all the data dependence relations and/or resource conflicts have been resolved. Thus, LNOPs can be removed in object codes for SVLIW processors. In this paper, we measure an improvement of the cache hit ratio caused by removing LNOPs in the object code. We also analyze an improvement of the processor performance due to higher cache hit ratio of the processor. Benchmark tests promise that the performance of SVLIW processors is improved more than 5% compared with that of traditional VLIW processors.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12B
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• pp.1967-1978
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• 2000

본 논문에서는 실행 시에 긴명령어를 구성하는 각 단위 명령어를 독립적으로 스케줄링할 수 있는 EIS 프로세서 구조를 제안하였다. 단위 명령어별 독립적인 수행을 위해서, EIS 프로세서 구조는 여러 개의 연산처리기와 스케줄러의 쌍으로 구성된다. EIS 프로세서 구조내의 모든 스케줄러는 독립적으로 자료종속성이나 자원충돌 여부를 검사하여 단위 명령어를 실행할지 혹은 다음 파이프라인 사이클동안 실행을 지연시킬지를 결정한다. 또한 EIS프로세서용 목적코드는 단위 명령어들간 동기화를 위해서 모든 단위 명령어에 종속성정보를 삽입하는 특징을 지닌다. 즉, EIS 프로세서 구조는 긴명령어내의 각 단위 명령어를 독립적으로 실행시킬 수 있으므로 기존의 VLIW 프로세서 구조나 SVLIW 프로세서 구조에서의 실행지연 시간을 제거할 수 있다. 시뮬레이션을 통해서도 EIS 프로세서 구조의 실행사이클이 VLIW 프로세서 구조나 SVLIW 프로세서 구조에서의 경우보다 더 빠름을 입증할 수 있었다. 특히 실수 명령어 분포가 높은 프로그램에서 EIS 프로세서에서의 실행사이클이 다른 프로세서 구조의 경우에 비하여 현저하게 줄어드는 것을 확인할 수 있었다.