• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.773-776
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• 2014

In this work, analog performances of silicon nanowire MOSFET with different length and channel width have been measured. The channel widths are 20nm, 30nm, 80nm, 130nm and lengths are 250nm, 300nm, 350nm, 500nm. temperatures $30^{\circ}C$, $50^{\circ}C$, $75^{\circ}C$, $100^{\circ}C$ have been measured. The trans-conductance, early voltage, gain, drain current and mobility have been characterized as a function of temperature. The mobility has been enhanced with wider channel width but it has been reduced with longer length and higher temperature. The trans-conductance has been increased with wider channel width. The early voltage has been enhanced with increase of gate length and temperature but it has been reduced with wider width. Therefore, gain has been enhanced with increase of gate longer length and wider width but it has been reduced with higher temperature.