• 한국재료학회지
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• 제14권6호
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• 대한금속재료학회지
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• 제46권1호
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.11-12
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• 2007

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2005년도 춘계학술발표대회 및 제8회 신소재 심포지엄 논문개요집
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• pp.53-53
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• 2005

• 전자통신동향분석
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• 제5권1호
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.2023-2025
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• 2002

We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

• 센서학회지
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• 제11권1호
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• pp.54-59
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• 2002

본 논문은 Si기판 직접접합기술과 전기화학적 식각정지를 이용하여 마이크로 시스템용 매몰 공동을 갖는 SOI 구조물의 일괄제조에 대한 새로운 공정기술에 관한 것이다. 저비용의 전기화학적 식각정지법으로 SOI의 정확한 두께를 제어하였다. 핸들링 기판 위에서 Si 이방성 습식식각으로 공동을 제조하였다. 산화막을 갖는 두 장의 Si기판을 직접접합한 후, 고온 열처리($1000^{\circ}C$, 60분)를 시행하고 전기화학적 식각정지로 매몰 공동을 갖는 SDB SOI 구조를 박막화하였다. 제조된 SDB SOI 구조물 표면의 거칠기는 래핑과 폴리싱에 의한 기계적인 방법보다도 우수했다. 매몰 공동을 갖는 SDB SOI 구조는 새로운 마이크로 센서와 마이크로 엑츄에이터에 대단히 효과적이며 다양한 응용이 가능한 기판으로 사용될 것이다.

• 한국진공학회지
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• 제17권2호
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• pp.156-159
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• 2008

Pseudo-MOSFET 방법을 이용하여 Ge농도에 따른 SiGe-on-Insulator(SGOI) 기판의 특성을 평가하였다. SGOI 기판은 compressive-SiGe / Relaxed-Si / Buried oxide / Si-substrate 구조로 SOI 기판 위에 에피택셜 성장법으로 SiGe층을 형성하였으며 compressive SiGe층의 Ge 농도는 각각 16.2％, 29.7％, 34.3％, 56.5％ 이다. 실험결과 Ge 농도가 증가함에 따라 누설전류가 증가하는 특성을 보였으며 threshold voltage는 nMOSFET의 경우 3V에서 7V로 이동하였으며 pMOSFET의 경우도 -7 V에서 -6 V로 이동하는 특성을 보였다. 급속 열처리 공정 (rapid thermal anneal) 후에 매몰 산화층과 기판 계면간의 스트레스에 의한 포획준위가 발생하여 소자특성이 열화되었지만, $H_2/N_2$ 분위기에서 후속 열처리 공정 (post RTA anneal) 을 통하여 계면 간의 포획준위를 감소시켜 SGOI Pseudo-MOSFET의 전기적 특성이 개선되었다.