• Korean Journal of Materials Research
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• v.9 no.9
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• pp.890-895
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• 1999

The recent important issue in solar cell fabrication is to adopt thin film silicon solar cells on cheap substrates. However, thin cells demand new grid design concept that all the contacts(to the emitter and base) be located on the front surface. Hence, the aim of the investigation presented in this paper was to determine the potential and the basic limitation of the design. With this concept, an interdigitated front grid structure was realized and cells were fabricated through a set of photolithography processes. Confirmed efficiencies of up to 11.5% were achieved on bonded SOI wafers with a cell thickness of 50$\mu\textrm{m}$ in the case of finger spacing more than $\mu\textrm{m}$ and a base width of 35$\mu\textrm{m}$. It was also shown from the results that the design rules for optimizing the base fraction and reducing the shadowing fraction are noted as an important technique to realize high-efficiency thin silicon solar cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.24-31
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• 2003

Short channel effects (SCE) of bulk MOSFET with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFET have been analyzed using a evanescent-mode analysis. Analytical equations of the characteristics scaling-length (λ) for three structures have been derived and the accuracy of the calculated λ was verified by comparing to the device simulation result. It is found that the minimum channel length should be larger than 5λ and the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70 nm CMOS technology. High-$textsc{k}$ dielectric shows a limitation in scaling due to the drain-field penetration through the dielectric unless the equivalent SiO2 thickness is very thin.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.276-281
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• 2000

Silicon carbide(SiC) films were grown on modified Si(111) surface with a SiNx in the NH$_3$surrounding. Thickness of SiC films was decreased with increasing of the nitridation time. Also, voids having crystal defects were removed at interface of SiC/Si according to growth parameters. SiC films were grown on SiNx/Si substrate of 100, 300 and 500nm thickness. SiC films were deposited along [111] direction and columnar grains of SiC crystal. The void-free film was observed in the interface of SiC/SiNx. This result suggests that fabrication of SiC devices are applied to SiNx replacing silicon oxide in SOI structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1890-1892
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.713-716
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• 2013

The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.1-8
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• 2002

In this paper, a thermopile which is applied to wide uses of temperature measuring was fabricated and its characteristic was improved by appling SOI structure to the fabrication. We improved characteristic of the thermopile by using single crystal silicon strips that has high seebeck coefficient and dielectric isolating the silicon strips from substrate with silicon dioxide film which dramatically decrease thermal conductivity between hot and cold junction compared to a silicon strip which was fabricated by ion implantation. The thermopile consists of 17 p-type single crystal silicon strips and 17 n-types by serial connection. The result of electromotive force measuring showed very good characteristic as 130mV/K when temperature difference between the two ends of the thermopile occurs by applying light on the thermopile fabricated with silicon strips of $1600{\mu}m$ length, $40{\mu}m$ width, $1{\mu}m$ thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.