• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.362-365
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• 1999

This paper describes on thinning SDB SOI substrates by SDB technology and electrochemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic substrates were analyzed by using AFM and SEM, respectivelv.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.54-59
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• 2002

This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.249-251
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• 2003

This paper discribes the analysis of the breakdown voltage characteristics of SOI LIGBT with dual epi-layer. In case of SOI LIGBT with dual epi-layer, if we used high doping concentration in epi-layer, we obtained higher breakdown voltage compared with typical device because of charge compensation effect, and we obtained low on-state resistivity characteristic in the same breakdown voltage. In this paper, we analyzed on-state and off-state characteristics of SOI LIGBT with dual epi-layer. Breakdown voltage of proposed LIGBT was shown 125V when $T_1=T_2=2.5{\mu}m$, $N_1=7{\times}10^{15}/cm^3$ and $N_2=3{\times}10^{15}/cm^3$, respectively Although we used high doping concentration and thin epi-layer thickness, breakdown voltage was increased compared with conventional devices.

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• Journal of the Semiconductor & Display Technology
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• v.7 no.1
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• pp.47-51
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• 2008

The Al:Au double-layer metal electrode for use in transparent, dual emission of organic light-emitting diode (OLED) was fabricated. The electrode of Al:Au metals with various thicknesses was deposited by the vacuum thermal evaporation technique. For Al thickness of 1 nm, a bottom luminance of $4880\;cd/m^2$ was observed at 8 V. Otherwise, top luminance of $2020\;cd/m^2$ were observed at 8 V. In addition, the threshold voltages of the electrodes were 2.2 V. It was forward that the inserting 1 nm Al between LiF and Au enhanced electron injection with tunneling effect.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.145-145
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• 2010

반도체 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 메모리 소자 또한 미세화를 위해 새로운 기술을 요구하고 있다. 1T DRAM은 하나의 트랜지스터와 하나의 캐패시터 구조를 가진 기존의 DRAM과 달리, 캐패시터 영역을 없애고 하나의 트랜지스터만으로 동작하기 때문에 복잡한 공정과정을 줄일 수 있으며 소자집적화에도 용이하다. 또한 SOI (Silicon-On-Insulator) 기판을 사용함으로써 단채널효과와 누설전류를 감소시키고, 소비전력이 적다는 이점을 가지고 있다. 1T DRAM은 floating body effect에 의해 상부실리콘의 중성영역에 축적된 정공을 이용하여 정보를 저장하게 된다. floating body effect를 발생시키기 위해 본 연구에서는 SOI 기판을 사용한 MOSFET을 사용하였는데, SOI 기판은 불순물 도핑농도에 따라 상부실리콘의 공핍층 두께가 결정된다. 실제로 불순물을 $10^{15}cm^{-3}$ 정도 도핑을 하게 되면 완전공핍된 SOI 구조가 된다. 이는 subthreshold swing값이 작고 저전압, 저전력용 회로에 적합한 특성을 보이기 때문에 부분공핍된 SOI 구조보다 우수한 특성을 가진다. 하지만, 상부실리콘의 중성영역이 완전히 공핍되어 정공이 축적될 공간이 존재하지 않게 된다. 이를 해결하기 위해 기판에 전압을 인가 후 kink effect를 확인하여, 메모리 소자로서의 구동 가능성을 알아보았다. 본 연구에서는 상부실리콘의 두께가 감소함에 따라 1T DRAM의 메모리 특성변화를 관찰하고자, TMAH (Tetramethy Ammonuim Hydroxide) 용액을 이용한 습식식각을 통해 상부실리콘의 두께가 각기 다른 소자를 제작하였다. 제작된 소자는 66 mv/dec의 우수한 subthreshold swing 값을 나타내며 빠른 스위칭 특성을 보였다. 또한 kink effect가 발생하는 최적의 조건을 찾고, 상부실리콘의 두께가 메모리 소자의 쓰기/소거 동작의 경향성에 미치는 영향을 평가하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)