• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.3-4
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• 2006

In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.711-714
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• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• 한국재료학회지
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• 제2권3호
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• pp.180-190
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• 1992

ZMR공정에서 발생하기 쉬운 폴리실리콘의 엉김현상(agglomeration), 슬림, 그리고 실리콘기판이 국부적으로 녹는 현상 등을 방지하기 위한 방법과 재결정화된 박막의 질을 향상시키기 위하여 폴리실리콘과 보호 산화막(capping oxide)두계를 변화시킨 실험 결과를 서술한다. 폴리실리콘의 엉김현상은 폴리실리콘과 보호 산화막 그리고 폴리실리콘과 매몰 산화막(buried oxide)의 계면에서의 wetting각과 관계되는데, 엉김현상을 방지하기 위해서는 암모니아 가스 분위기에서 $1100^{\circ}$C, 3시간 동안 열처리하여 폴리실리콘과 보호 산화막 그리고 폴리실리콘과 매몰 산화막의 계면에 질소를 주입시키면 된다. 실리콘 기판의 뒷면이 국부적으로 녹아 SOI구조가 파괴되는 현상과 슬립은 실리콘 기판의 뒷면을 모래타격(sandblast)하여 약 $20{\mu}m$의 거칠기를 가지도록 했을때 방지할 수 있었다. 재결정화된 폴리실리콘의 두께가 두꺼워짐에 따라 재결정화된 박막에서 subboundary의 간격은 넓어지고, 재결정화된 실리콘 두께의 균일성은 보호 산화막이 두꺼울수록 향상된다. 폴리실리콘의 두께를 $1{\mu}m$로 하였을때 subboundary의 간격은 약 $70-120{\mu}m$정도였고 폴리실리콘의 두께가 $1{\mu}m$이고 보호산화막의 두께가 $2.5{\mu}m$일때, 재결정화 후 실리콘의 두게 균일도는 약 ${\pm}200{\AA}$정도였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• 전자공학회논문지A
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• 제31A권12호
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• pp.100-105
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• 1994

SOI(Silicon-On-Insulator) pn 다이오드의 최적 수평길이($L_{dr}$)와 항복전압에 대한 해석적인 표현식을 n' 츠리프트 영역의 농도 및 두께, 매몰 산화막 두께의 함수로 유도하였다. 최적($L_{dr}$은 n'n접합의 수직 방향전계에 의한 항복전압과 n'np'접합으 수평방향 전계에 의한 항복전압이 같다는 조건으로부터 유도하였다. 해석적 표현식의 결과는 PISCESII를 사용한 시뮬레이션 결과와 잘 일치하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권6호
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• pp.303-306
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• 2001

STFR were fabricated on the floating membrane which was formed by SOI-micromachining process. The floating membranes having a thickness range of $3{\sim}15{\mu}m$ could be simply formed by micromachining the directly-bonded and thinned SOI substrate. The STFR device fabricated on the $15{\mu}m$-thick membrane showed resonance frequency of fr = 1.65 GHz, coupling coefficient of Keff2 = 2.4 %, and series and parallel quality factors of Qs = 91.7 and Qp = 87.7, respectively.