• Proceedings of the Materials Research Society of Korea Conference
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• 2005.05a
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• pp.53-53
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• 2005

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1621-1623
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• 1997

The breakdown voltage of SOI RESURF (REduce SURface Field) diode using a SIPOS (Semi Insulating POlycrystalline Silicon) layer is verified in terms of n-drift layer length and surface oxide thickness by device simulator MEDICI, and compared with conventional SOI RESURF diode. Increasing the n-drift layer length, the breakdown voltage of SOI RESURF diode using the SIPOS layer have increased and saturated at $8{\mu}m$. And it has decreased with increasing the surface oxide thickness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.7-8
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness ($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. The enhancement of effective hole mobility at the effective field of 0.1 MV/ccm was observed from 3-nm to 5-nm SOI thickness range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.2010-2015
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• 1989

A SOI was fabricated by the FIPOS technique using n/p+/p silicon structure. Fabricated silicon island which has 3\ulcorner thickness and 100\ulcorner width was investigated by measuring van der Pauw resistivity, Hall mobility, dielectric breakdown voltage and leakage current. Hall mobility of the SOI was measured to be 300-500cm\ulcornerV.sec and its breakdown field was 1-2 MV/cm. The cross-sectional geometries of the SOI island were examined by SEM and optical microscope.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.545-548
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• 1998

Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.192-194
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• 1993

In this paper, a silicon piezoresistive accelerometer of which the cantilevers have uniform thickness is designed and fabricated with SOI wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW etchant. The fabrication processes are that of the frontside processes including the etching of the cantilevers and the doubleside alignment holes, the diffusion of the piezoresisters and patterning of the contact windows, and the metal connection process, and that of the backside processes including the etching of the shallow cavity and the seismic mass. Because of the uniformity of thickness, the performance of the accelerometer fabricated with SOI wafer is expected to be better than that of accelerometer fabricated by the time-controlled etching method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.583-586
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• 2000

The non-selective method by polishing after grinding was used widely to thinning of SDB SOI structures. This method was very difficult to thickness control of thin film, and it was dependent on equipments. However electrochemical etch-stop, one of the selective methods, was able to accurately thickness control and etch equipment was very simple. Therefore, this paper described with the effect of leakage current and electrodes on electrochemical etch-stop. Consequentially, PP(passivation potential) was changed according to the kinds of contact and contact sizes, but OCP(open current potential) was not change with range of -1.5~-1.3V