• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.9-14
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• 2004

This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.250-255
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• 2000

본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.719-722
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• 2003

This work investigates the device degradation p-channel PD SOI devices at various applied voltages as well as stress temperatures with respect to Body-Contact SOI (BC-SOI) and Floating-Body SOI (FB-SOI) MOSFETs. It is observed that the drain current degradation at the gate voltage of the maximum gate current is more significant in FB-SOI devices than in BC-SOI devices. For a stress at the gate voltage of the maximum gate current and elevated temperature, it is worth noting that the $V_{PT}$ Will be decreased by the amount of the HEIP plus the temperature effects. For a stress at $V_{GS}$ = $V_{DS}$ . the drain current decreases moderately with stress time at room temperature but it decreases significantly at the elevated temperature due to the negative bias temperature instability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• ETRI Journal
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• v.9 no.1
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• pp.146-157
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• 1987

SOI(Silicon-On-Insulator)는 차세대 VLSI 구조로서 최근 중요한 연구개발 대상이 되고 있다. SOI의 제조기술을 크게 recrystallization, ELO, FIPOS 및 SIMOX로 나누고 이들 각 기술에 대한 고찰을 하였다. 향후 전반적인 SOI 제조기술 개발방향은 SOI면적 확장 및 결함 감소를 위한 것이 될 것이다.