• 제목/요약/키워드: SOC Verification

검색결과 45건 처리시간 0.027초

SOC Bus Transaction Verification Using AMBA Protocol Checker

  • Lee, Kab-Joo;Kim, Si-Hyun;Hwang, Hyo-Seon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권2호
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    • pp.132-140
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    • 2002
  • This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

집적검증 기법을 채용한 하드웨어/소프트웨어 동시검증 (Hardware/Software Co-verification with Integrated Verification)

  • 이영수;양세양
    • 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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    • 제8권3호
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    • pp.261-267
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    • 2002
  • SOC(System On a Chip)에 대한 설계에서 설계 생산성을 향상시키기 위해서 가장 시급히 해결해야 할 과제가 하드웨어뿐만 아니라 소프트웨어가지도 함께 동시검증(co-verification)하여야 함으로서 설계검증에 과도하게 투입되는 비용과 시간을 줄이는 것이다. 본 논문에서는 이러한 설계검증 생산성을 효과적으로 높이기 위한 방법으로 HW/SW 동시검증을 수행할 수 있는 대표적인 두 방법들인 동시-시뮬레이션(co-simulation)과 동시-에뮬레이션(co-emulation)을 강하게 결합한 새로운 검증 방법인 집적 동시검증(integrated co-verification) 방법을 제안하였다. 또한, 상용화된 동시검증 툴인 Seamless CVE와 물리적 프로토타이핑 보드를 함께 사용하여 구성한 ARM/AMBA 플랫폼 기반의 집적 동시검증 환경을 직접 구성하고, 이를 이용하여 제안된 검증기법의 유용성을 실험적으로 확인하였다.

DIVERSITY DESIGN FOR SENSOR DATA ACQUISITION AT COMS SOC

  • Park, Durk-Jong;Koo, In-Hoi;Ahn, Sang-Il
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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    • pp.479-481
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    • 2007
  • COMS will transmit its observed data, Sensor Data, through L-Band with linear polarization. To avoid link loss caused by polarization discrepancy between satellite and SOC DATS, the L-Band antenna at SOC DATS should be linearly polarized. However, SOC DATS is supposed to share single antenna with SOC TTC, so the antenna should be circularly polarized. To cope with about 3dB loss, SOC DATS is designed to receive Sensor Data through two orthogonal circular polarizations, RHCP (Right-Hand Circular Polarization) and LHCP (Left-Hand Circular Polarization). Eventually, SOC DATS can obtain 2.6dB of combining gain through diversity combiner in MODEM/BB. This paper presents the verification on the diversity combining of SOC DATS with test configuration and results in depth.

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A Simplified Li-ion Battery SOC Estimating Method

  • Zhang, Xiaoqiang;Wang, Xiaocheng;Zhang, Weiping;Lei, Geyang
    • Transactions on Electrical and Electronic Materials
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    • 제17권1호
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    • pp.13-17
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    • 2016
  • The ampere-hour integral method and the open circuit voltage method are integrated via the extended Kalman filter method so as to overcome insufficiencies of the ampere-hour integral method and the open circuit voltage method for estimating battery SOC. The process noise covariance and the measurement noise covariance of the extended Kalman filter method are simplified based on the Thevenin equivalent circuit model, with a proposed simplified SOC estimating method. Verification of DST experiments indicated that the battery SOC estimating method is simple and feasible, and the estimated SOC error is no larger than 2%.

SOC Verification Based on WGL

  • Du, Zhen-Jun;Li, Min
    • 한국멀티미디어학회논문지
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    • 제9권12호
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    • pp.1607-1616
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    • 2006
  • The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.

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임베디드 보드를 사용한 EKF 기반 실시간 배터리 SOC 추정 (Real-time EKF-based SOC estimation using an embedded board for Li-ion batteries)

  • 이현아;홍선리;강모세;신단비;백종복
    • 전기전자학회논문지
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    • 제26권1호
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    • pp.10-18
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    • 2022
  • 정확한 SOC 추정은 배터리 운영 전략을 제시하는 중요한 지표로 많은 연구가 진행되었다. 기존 연구에서 검증을 위해 주로 사용되던 시뮬레이션 방식은 실제 BMS 환경처럼 실시간 SOC를 추정하기 어렵다. 따라서 본 논문에서는 실시간 배터리 SOC 추정이 가능한 임베디드 시스템을 구현하고 검증 과정에서 발생 가능한 문제 분석을 목표로 한다. 2개의 라즈베리파이 보드로 구성된 환경은 Simscape 배터리에서 측정된 데이터로 EKF 기반 SOC 추정을 진행한다. 검증 단계에서는 온도에 따라 달라지는 배터리 특성을 고려하여, 다양한 주변 온도에서 결과를 확인하였다. 또 임베디드 환경에서 발생하는 오프셋 오류와 패킷 손실에 대비하여, 문제 상황에서 SOC 추정 성능을 검증하였다. 이를 통해 안정범위의 5%내의 오차를 갖는 실시간 SOC 추정이 가능한 임베디드 시스템 구현을 위한 전략을 제시한다.

MMAE-EKF를 이용한 SOC 추정 알고리즘 구현 및 검증 (Implementation and Verification of SOC Estimation Algorithm using MMAE-EKF)

  • 윤현용;김동주;신승민;김민국;이병국
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2013년도 추계학술대회 논문집
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    • pp.222-223
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    • 2013
  • 본 논문에서는 배터리 SOC 추정 정확도 향상을 위해 기존 EKF 추정 기법에 MMAE 방법을 접목시키는 방법을 제안한다. 노이즈의 세기에 따라 EKF 출력에 비중을 부여함으로써 배터리 사용 전 영역에서 SOC 추정 오차 저감이 가능하며, Matlab 시뮬레이션을 통하여 MMAE-EKF 알고리즘의 타당성을 검증하였다.

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VERIFICATION ON THE PERFORMANCE OF COMS SOC S-BANDSSPA

  • Park, Durk-Jong;Yang, Hyung-Mo;Ahn, Sang-Il
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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    • pp.482-485
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    • 2007
  • The S-Band SSPA is front-end equipment to transmit both LRIT and HRIT to COMS. To provide the required EIRP, S-Band SSPA is designed to generate maximum 1kW power at its 1dB gain compression point (P1dB). Due to the operation for 24 hours per seven days, the verification on the performance of S-Band SSPA was performed thoroughly. This paper presents that major requirements such as maximum 1kW power, maximum -26dBc of IMD characteristic at 500W output and around -57dBc of coupling factor were verified through proposed test configuration.

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An experimental study on the development and verification of NCC(new concrete cutting) system

  • Park, Jong-Hyup;Han, Jong-Wook
    • Structural Engineering and Mechanics
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    • 제65권2호
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    • pp.203-211
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    • 2018
  • This paper introduces the development process of NCC(New Concrete Cutting) system and analyzes first verification test. Based on the first verification test results, some problems of NCC system have been newly modified. We carry out the second verification test. We tried to verify cutting performance and dust control efficiency of NCC system through the cutting test of concrete bridge piers. In particular, this verification test strives to solve the problem of concrete dust, which is the biggest problem of dry cutting method. The remaining dust problems in cutting section tried to solve through this verification test. This verification test of the NCC system shows that the dust problem of dry cutting method is closely controlled and solved. In conclusion, the proposed NCC method is superior to the dry cutting method in all aspects, including cutting performance, dust vacuum efficiency and cooling effect. The proposed NCC system is believed to be able to provide eco-friendly cutting technology to various industries, such as the removal of the SOC structures and the dismantling of nuclear plants, which have recently become a hot issue in the field of concrete cutting.