• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.479-481
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• 2007

COMS will transmit its observed data, Sensor Data, through L-Band with linear polarization. To avoid link loss caused by polarization discrepancy between satellite and SOC DATS, the L-Band antenna at SOC DATS should be linearly polarized. However, SOC DATS is supposed to share single antenna with SOC TTC, so the antenna should be circularly polarized. To cope with about 3dB loss, SOC DATS is designed to receive Sensor Data through two orthogonal circular polarizations, RHCP (Right-Hand Circular Polarization) and LHCP (Left-Hand Circular Polarization). Eventually, SOC DATS can obtain 2.6dB of combining gain through diversity combiner in MODEM/BB. This paper presents the verification on the diversity combining of SOC DATS with test configuration and results in depth.

• IT SoC Magazine
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• s.19
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• pp.48-48
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• 2007

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.13-17
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• 2016

The ampere-hour integral method and the open circuit voltage method are integrated via the extended Kalman filter method so as to overcome insufficiencies of the ampere-hour integral method and the open circuit voltage method for estimating battery SOC. The process noise covariance and the measurement noise covariance of the extended Kalman filter method are simplified based on the Thevenin equivalent circuit model, with a proposed simplified SOC estimating method. Verification of DST experiments indicated that the battery SOC estimating method is simple and feasible, and the estimated SOC error is no larger than 2%.

• Journal of Korea Multimedia Society
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• v.9 no.12
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• pp.1607-1616
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• 2006

The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.

• Journal of IKEEE
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• v.26 no.1
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• pp.10-18
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• 2022

Accurate SOC estimation is an important indicator of battery operation strategies, and many studies have been conducted. The simulation method which was mainly used in previous studies, is difficult to conduct real-time SOC estimation like real BMS environment. Therefore, this paper aims to implement a real-time battery SOC estimation embedded system and analyze problems that can arise during the verification process. In environment consisting of two Raspberry Pi boards, SOC estimation with the EKF uses data measured by the Simscape battery model. Considering that the operating characteristics of the battery vary depend on the temperature, the results were analyzed at various ambient temperatures. It was confirmed that accurate SOC estimation was performed even when offset fault and packet loss occurred due to communication or sensing problems. This paper proposes a guide for embedded system strategies that enable real-time SOC estimation with errors within 5%.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.222-223
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• 2013

본 논문에서는 배터리 SOC 추정 정확도 향상을 위해 기존 EKF 추정 기법에 MMAE 방법을 접목시키는 방법을 제안한다. 노이즈의 세기에 따라 EKF 출력에 비중을 부여함으로써 배터리 사용 전 영역에서 SOC 추정 오차 저감이 가능하며, Matlab 시뮬레이션을 통하여 MMAE-EKF 알고리즘의 타당성을 검증하였다.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.482-485
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• 2007

The S-Band SSPA is front-end equipment to transmit both LRIT and HRIT to COMS. To provide the required EIRP, S-Band SSPA is designed to generate maximum 1kW power at its 1dB gain compression point (P1dB). Due to the operation for 24 hours per seven days, the verification on the performance of S-Band SSPA was performed thoroughly. This paper presents that major requirements such as maximum 1kW power, maximum -26dBc of IMD characteristic at 500W output and around -57dBc of coupling factor were verified through proposed test configuration.

• Structural Engineering and Mechanics
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• v.65 no.2
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• pp.203-211
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• 2018

This paper introduces the development process of NCC(New Concrete Cutting) system and analyzes first verification test. Based on the first verification test results, some problems of NCC system have been newly modified. We carry out the second verification test. We tried to verify cutting performance and dust control efficiency of NCC system through the cutting test of concrete bridge piers. In particular, this verification test strives to solve the problem of concrete dust, which is the biggest problem of dry cutting method. The remaining dust problems in cutting section tried to solve through this verification test. This verification test of the NCC system shows that the dust problem of dry cutting method is closely controlled and solved. In conclusion, the proposed NCC method is superior to the dry cutting method in all aspects, including cutting performance, dust vacuum efficiency and cooling effect. The proposed NCC system is believed to be able to provide eco-friendly cutting technology to various industries, such as the removal of the SOC structures and the dismantling of nuclear plants, which have recently become a hot issue in the field of concrete cutting.