• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.2C
• /
• pp.25-30
• /
• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.407-418
• /
• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• Journal of Broadcast Engineering
• /
• v.16 no.6
• /
• pp.1026-1035
• /
• 2011

This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.5 no.3
• /
• pp.169-173
• /
• 2012

This paper investigates the performance of Turbo equalization in wireless multipath channels. Turbo equalization mainly consists of a SISO(soft-in soft-out) equalizer and a SISO decoder. Iterative channel estimators can improve the accuracy of channel estimates by soft information fed back from the SISO decoder. Comparing iterative channel estimators with LMS(least mean square) and RLS(recursive least squares) algorithms, which are the most common algorithms to estimate and track a time-varying channel impulse response, the iterative channel estimator with RLS converges more faster than the one with LMS. However, the difference of BER(bit error rate) performances gradually decreases as the number of iterations for Turbo equalization increases.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.3C
• /
• pp.215-223
• /
• 2003

Turbo codes are selected as FEC(Forward error correction) codes with convolution code in 3GFP(3rd generation partnership project) and 3GPP2 standard of IMT2000. Especially, l/3 turbo code with K=4 is employed for 3GPP standard. In this paper, we proposed a hardware structure of a turbo decoder and denveloped the decoder for 3GPP standard turbo code. For its efficient operation, we design a SOVA decoder by employing a register exchange decoding block and new path metric normalization block as a SISO constituent decoder. In addition, we estimate its performance under MATLAB 6.0 and designed the turbo decoder including control block, input control buffer, SOVA constituent decoder with VHDL. Finally, we synthesized the developed turbo decoder under Synopsys FPGA Express and verified it with ALTERA EPF200SRC240-3 FPGA device.

• Journal of Broadcast Engineering
• /
• v.15 no.5
• /
• pp.665-671
• /
• 2010

In this paper, a turbo equalizer is proposed for the digital video broadcasting for terrestrial - 2nd generation (DVB-T2) system. The proposed turbo equalizer is consisted with the maximum a posteriori (MAP) and low density parity check (LDPC) decoder. The channel information for the soft-input-soft-output (SISO) MAP equalizer is based on the least square (LS) channel estimator. The performance is analyzed through computer simulations in terms of the iteration number.

• ETRI Journal
• /
• v.30 no.1
• /
• pp.113-128
• /
• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.2C
• /
• pp.175-180
• /
• 2009

When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.10
• /
• pp.850-857
• /
• 2013

Turbo equalizer system is a method which can improve performance through a combination of the equalizer and decoder. The turbo equalizer has been mainly used a MAP equalizer. However, this turbo equalizer has a disadvantage that has a high computational complexity. To overcome the disadvantage and to improve efficiency of bandwidth, blind turbo equalization system is proposed. blind turbo equalization system has low equalization performance than conventional turbo equalization system. To circumvent this problem, we adapt the beamforming method based on the MUSIC algorithm. we confirmed that the proposed method improves the equalization performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.5A
• /
• pp.423-430
• /
• 2010

The performances of turbo-coded space-time block coding (STBC) schemes are subject to how soft decision detection (SDD) information are generated from the STBC decoder. For this reason, we have to pay particular attention to estimation of SDD. In this paper, we evaluate the performance of a turbo coded STBC scheme depending on the accuracy of the SDD. Recently, a new quasi orthogonal STBC (QO-STBC) scheme using a noise whitened filter was proposed in order to reduce noise enhancing effect of zero forcing detection process. This QO-STBC scheme was proven to be efficient in computational complexity compared to the other conventional QO-STBC schemes. In this paper, we first present detailed mathematical analysis on the noise whitened QO-STBC scheme, and by using the result we propose the optimum SDD method.