• Title/Summary/Keyword: SHA-1

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Design and Implement of Security Module for Web Server and Client (웹 서버/클라이언트를 위한 보안 모듈 설계 및 구현)

  • 변용덕;장승주
    • Proceedings of the Korean Information Science Society Conference
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    • 2000.04a
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    • pp.178-180
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    • 2000
  • 현재의 인터넷을 통한 웹 서버/클라이너트 환경에서 보안과 신뢰성 문제는 나날이 증가하고 있다. 기술적인 측면에서는 이러한 문제점을 개선하기 위하여 서버는 기존의 Apache 웹 서버에 라이브러리 형태의 보안모듈을 추가하였다. 보안 모듈의 기능은 크라이언트의 요청이 발생하면 웹 문서에 대한 RSA 암호화 기능과 메시지의 무결성 검사를 위한 SHA-1기능과 키 생성을 위한 랜덤 키 생성 기능을 포함한다. 클라이언트는 기존의 웹 브라우저에 Winsock2의 LSP 기능을 이용하여 보안 모듈을 체인의 형태로 삽입함으로써 보안 상의 문제점을 개선하고자 한다. 클라이언트의 보안 모듈의 기능은 서버로부터 받은 암호화된 메시지에 대한 RSA 복호화 알고리즘과 메시지가 네트워크를 통해 전송되는 도중 변경되지 않았음을 증명하기 위한 SHA-1알고리즘을 포함한다. 그리고 사용자 편의성 측면에서 보안을 위한 새로운 소프트웨어의 설치와 기존의 프로그램 변경 없이 모듈을 추가, 삭제함으로써 사용자의 편리성을 추구 하였다.

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An Improved Fast and Secure Hash Algorithm

  • Agarwal, Siddharth;Rungta, Abhinav;Padmavathy, R.;Shankar, Mayank;Rajan, Nipun
    • Journal of Information Processing Systems
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    • v.8 no.1
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    • pp.119-132
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    • 2012
  • Recently, a fast and secure hash function SFHA - 256 has been proposed and claimed as more secure and as having a better performance than the SHA - 256. In this paper an improved version of SFHA - 256 is proposed and analyzed using two parameters, namely the avalanche effect and uniform deviation. The experimental results and further analysis ensures the performance of the newly proposed and improved SFHA-256. From the analysis it can be concluded that the newly proposed algorithm is more secure, efficient, and practical.

Design and Implementation of Disk Archive System Exploiting De-duplication Scheme (데이터 중복 제거 기반의 디스크 아카이브 시스템 설계 및 구현)

  • Kang, Sung-Woon;Jung, Ho-Min;Ko, Young-Woong;Lee, Jeong-Gun
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.204-206
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    • 2011
  • 기존의 TAR와 같은 아카이브 포맷은 파일의 중복을 제거하는 기능이 포함되지 않아 리눅스 배포 미러와 같이 버전단위로 저장되는 시스템에서 디스크 공간의 낭비가 발생했다. 본 연구에서는 중복 제거 기능이 포함된 아카이브 포맷인 DTAR와 이를 지원하는 DTM 유틸리티를 제안하였다. 주요 아이디어는 DTAR 헤더에 SHA1 해시를 삽입하고 SHA1 해시를 노드로 하는 R-B Tree를 생성하여 중복을 검색 및 제거하는 것이다. 실험 결과 DTAR가 tar.gz보다 최대 31% 공간을 절약하고, 수행 시간도 줄어드는 것을 확인하여 효율적임을 보였다.

Parallel Implementation of LSH Using SSE and AVX (SSE와 AVX를 활용한 LSH의 병렬 최적 구현)

  • Pack, Cheolhee;Kim, Hyun-il;Hong, Dowon;Seo, Changho
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.26 no.1
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    • pp.31-39
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    • 2016
  • Hash function is a cryptographic primitive which conduct authentication, signature and data integrity. Recently, Wang et al. found collision of standard hash function such as MD5, SHA-1. For that reason, National Security Research Institute in Korea suggests a secure structure and efficient hash function, LSH. LSH consists of three steps, initialization, compression, finalization and computes hash value using addition in modulo $2^W$, bit-wise substitution, word-wise substitution and bit-wise XOR. These operation is parallelizable because each step is independently conducted at the same time. In this paper, we analyse LSH structure and implement it over SIMD-SSE, AVX and demonstrate the superiority of LSH.

A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference

  • Hwang, Dong-Hyun;Song, Jung-Eun;Nam, Sang-Pil;Kim, Hyo-Jin;An, Tai-Ji;Kim, Kwang-Soo;Lee, Seung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.2
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    • pp.98-107
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    • 2013
  • This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

Implementation of Validation Tool for Cryptographic Modules (암호기술 구현물 검증도구 구현)

  • 이종후;김충길;이재일;이석래;류재철
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.2
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    • pp.45-58
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    • 2001
  • There are relatively many research results of the validation of the cryptography. But few researches on the validation of cryptography implementations were accomplished. However, developer\`s misunderstanding the crypto-algorithm or a mistake in implementation of the crypto-a1gorithm leads to lose reliability of security products. Therefore, as validation of the crypto-algorithm itself also validation of the implementation is important. The major objective of this paper is to propose Security Products Validation Tool. Our tool validates implementation of the public key algorithm (RSA. KCDSA) and hash algorithm (SHA-1, HAS-170). The validation process is composed of several items and our tool performs validation teats for conformance to related standard.

A Diagnosis of Ecological Health Using a Physical Habitat Assessment and Multimetric Fish Model in Daejeon Stream (물리적 서식지평가기법 및 어류 다변수 평가모델에 의거한 대전천의 생태학적 건강도 진단)

  • Kim, Ja-Hyun;An, Kwang-Guk
    • Korean Journal of Ecology and Environment
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    • v.38 no.3 s.113
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    • pp.361-371
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    • 2005
  • The objective of study was to diagnose integrative ecological health of Daejeon Stream, one of the tributaries of Guem River, during May 2004 ${\sim}$ April 2005. The research approach was primarily based on a Qualitative Habitat Evaluation Index (QHEI) and the Index of Biological Integrity (IBI) using fish assemblage. These outcomes were compared with conventional chemical dataset. For the experiment, four sampling sites were chosen from Daejeon Stream and long-term water quality data during 1995 ${\sim}$ 2004 (obtained from the Ministry of Environment) were analyzed in the spatial and temporal aspects. For the biological health assessment, we developed a stream health assessment model (SHA model) far regional applications. We found that current water quality conditions, based on the COD, BOD, TN and TP, were enhanced by 1.6 ${\sim}$ 5.3 fold over the period of 1995 ${\sim}$ 2004 and that the parameters showed a typical longitudinal decline from the upstream to downstream reach. The differences of water quality between the two reaches were more than 4.4 times, indicating a large spatial variations within the stream. The health conditions, based on the SHA model, averaged 23 and varied from 20 to 26 depending on the sampling stations. Values of the QHEI varied from 39 (Poor condition) to 124 (Cood condition)and values of QHEI in the reach of S2 ${\sim}$ S4 had significantly lower than in the headwater site (S1). Also, biological stream health, based on the criteria of US EPA (1993), was judged as 'Poor condition', in the S4 where TN, TP, BOD and COD were highest. In the meantime, maximum value of SHA (26) was found in the upstream reach (S1) where the water quality and QHEI were best. We also found that compositions of sensitive species showed a linear function with water quality conditions and this pattern was evident in the tolerant species. Thus, the biological stream health, based on the SHA model, matched well water chemistry. Overall outcomes suggest that the biological health impact was a function of chemical degradation and physical habitat quality in the stream.

Low Power Implementation of Integrated Cryptographic Engine for Smart Cards (스마트카드 적용을 위한 저전력 통합 암호화 엔진의 설계)

  • Kim, Yong-Hee;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.80-88
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    • 2008
  • In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

Design and Performance Evaluation of the Secure Transmission Module for Three-dimensional Medical Image System based on Web PACS (3차원 의료영상시스템을 위한 웹 PACS 기반 보안전송모듈의 설계 및 성능평가)

  • Kim, Jungchae;Yoo, Sun Kook
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.3
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    • pp.179-186
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    • 2013
  • PACS is a medical system for digital medical images, and PACS expand to web-based service using public network, DICOM files should be protected from the man-in-the-middle attack because they have personal medical record. To solve the problem, we designed flexible secure transmission system using IPSec and adopted to a web-based three-dimensional medical image system. And next, we performed the performance evaluation changing integrity and encryption algorithm using DICOM volume dataset. At that time, combinations of the algorithm was 'DES-MD5', 'DES-SHA1', '3DES-MD5', and '3DES-SHA1, and the experiment was performed on our test-bed. In experimental result, the overall performance was affected by encryption algorithms than integrity algorithms, DES was approximately 50% of throughput degradation and 3DES was about to 65% of throughput degradation. Also when DICOM volume dataset was transmitted using secure transmission system, the network performance degradation had shown because of increased packet overhead. As a result, server and network performance degradation occurs for secure transmission system by ensuring the secure exchange of messages. Thus, if the secure transmission system adopted to the medical images that should be protected, it could solve server performance gradation and compose secure web PACS.

A Design of 12-bit 100 MS/s Sample and Hold Amplifier (12비트 100 MS/s로 동작하는 S/H(샘플 앤 홀드)증폭기 설계)

  • 허예선;임신일
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.133-136
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    • 2002
  • This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

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