• Journal of Internet of Things and Convergence
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• v.2 no.3
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• pp.43-51
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• 2016

In this paper, we have developed Crypft+ as an enhanced file encryption/decryption system to improve the security of IoT system or individual document file management process. The Crypft+ system was developed as a core security module using Python, and designed and implemented a user interface using PyQt. We also implemented encryption and decryption function of important files stored in the computer system using AES based symmetric key encryption algorithm and SHA-512 based hash algorithm. In addition, Cx-Freezes module is used to convert the program as an exe-based executable code. Additionally, the manual for understanding the Cryptft+ SW is included in the internal program so that it can be downloaded directly.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.459-460
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• 2017

해시 함수는 데이터의 위변조를 확인하기 위해 사용하는 일방향 함수로, 현재 많은 기술 및 논문에서 해시 함수를 사용하고 있다. 대표적인 해시 함수에는 MD와 SHA가 있으며 다양한 버전을 가지고 있다. 본 논문에서는 해시 알고리즘들의 안전성과 관련된 동향과 취약점을 파악하고 향후 방향성을 알아보고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.146-153
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• 2001

A new password authentication method Is proposed in this paper for the purpose of providing web page authors the convenience in deploying password-protected Web realms at a web server. According to this method. a web realm is mapped to a secret directory at the web server. in which access-controlled web pages are stored. A password is used to construct the name of the secret directory. A javaScript code is embedded in a sign-in web pageoutside the secret directory, which converts the user-entered password into the directory name and forms a complete URL pointing to an access-controlled web page inside the secret directory. Thus, only users knowing the password can compose a valid URL and retrieve the access-controlled web page. Using this method, web page authors can deploy password-protected web realms in a server-independent manner.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.356-359
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• 2007

Writable Cholesteric Liquid Crystal Display and the algorithm used to detect its image were developed. We could use any hard tip, ex: the tip of a forefinger, to directly write an image on the surface of Cholesteric Liquid Crystal Display (CHLCD). By measuring the capacitance of one pixel of test cell (12mm x 15mm/1x1), F-state or P-state could be detected. By measuring the capacitance of one pixel of 4.1" CHLCD (241um x 241um/ 320x320), F-state or Pstate could not be detected, due to the effect of parasitic capacitance. Therefore, high frequency measurement and the algorithm were developed to detect the image on CHLCD.

• Journal of the Optical Society of Korea
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• v.18 no.1
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• pp.82-88
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• 2014

A binary-coupled dipole approximation (BCDA) is described for designing metal nanoparticles with nonperiodic structures in one, two, and three dimensions. This method can be used to simulate the variation of near- and far-field properties through the interactions of metal nanoparticles. An advantage of this method is in its combination with the binary particle swarm optimization (BPSO) algorithm to find the best array of nanoparticles from all possible arrays. The BPSO algorithm has been used to design an array of plasmonic nanospheres to achieve maximum absorption, scattering, and extinction coefficient spectra. In BPSO, a swarm consists of a matrix with binary entries controlling the presence ('1') or the absence ('0') of nanospheres in the array. This approach is useful in optical applications such as solar cells, biosensors, and plasmonic nanoantennae, and optical cloaking.

• Journal of Korea Multimedia Society
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• v.11 no.6
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• pp.845-851
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• 2008

The ID/password method is the most classical method among authentication techniques on the internet, and is performed more easily and successfully than other methods. However, it is a vulnerable method against attacks such as eavesdropping or replay attack. To overcome this problem, OTP technique is used. The most popular OTP is HOTP algorithm, which is based on one-way hash function SHA-1. As recent researches show the weakness of the hash function, we need a new algorithm to replace HOTP. In this paper we propose a new OTP algorithm using the MAC(Message Authentication Code) based on AES. We also show that the new OTP outperforms HOTP experimentally.

• Journal of Internet Computing and Services
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• v.1 no.2
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• pp.11-18
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• 2000

In this paper we present a new extensible model based upon the concept of subtransactions in real-time transaction systems. The nested transaction model originally proposed by J. Moss is extended for real-time uniprocessor transaction systems by adding explicit timing constraints. Based upon the model, an integrated concurrency control and scheduling algorithm is developed, that not only guarantees timing constraints of a set of real-time transactions but also maintains consistency of the database. The algorithm is based on the priority ceiling protocol of Sha et al. We prove that the Real-Time Nested Priority Ceiling Protocol prevents unbounded blocking and deadlock, and maintains the serializability of a set of real-time transactions. We use the upper bound on the duration that a transaction can be blocked to show that it is possible to analyze the schedulability of a transaction set using rate-monotonic priority assignment. This work is viewed as a step toward multiprocessor and distributed real-time nested transaction systems. Also, it is possible to be extended to include the real-time multimedia transactions in the emerging web-based database application areas.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.65-73
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• 2008

Security layer of the Cdma2000 1x EV-DO is currently completing standard (C.S0024-A v2.0). Accordingly, a hardware security devices, that allows to implementation requirement of the security layer described in standard document, is required to apply security function about data transferred between AT and AN of then Cdma2000 1x EV-DO environment. This paper represents design of hardware device providing EV-DO security with simulation of the security layer protocol via the FPGA platform. The SHA-1 hash algorithm for certification and service of packet data, and the AES, SEED, ARIA algorithms for data encryption are equip in this device. And paper represents implementation of hardware that applies optionally certification and encryption function after executing key-switch using key-switching algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.