• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.67-71
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• 2011

Existing face detection systems, which are used for digital door locks, digital cameras, video surveillance systems, and so on, are software-based implementation for relatively low level resolution images. Therefore, in this case, there are difficulties in detecting faces in a real-time fashion due to the increasing amount of operational processing as well as in allowing the requirements of face detections for HD(High Definition) resolutions. A hardware approach is necessary to efficiently find faces for HD images in real-time embedded systems. This paper proposes and implements a hardware architecture for an LBP(Local Binary Pattern) operation which is a time-consuming part as one of preprocessing steps for face detection. The hardware architecture proposed in this research has been implemented and tested with a FPGA(Field Programmable Gate Array) chip, and shown that the approach guarantees efficient face detection for HD images.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.78-91
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• 2012

The Terrestrial DTV service compliant with ATSC has been advancing for years. In KBA(Korean Broadcasters Association), a multi-channel service was broadcasted on air during the period of the 2006 FIFA World Cup Germany with the various type of MMS(Multi Mode Service) using MPEG-2 encoding method. MMS Service can provides not only one HD channel but also serveral additional services within 6MHz bandwidth. Using digital video compression technology(MPEG-2), many various programs such as HDTV, SDTV, Audio and Data are able to be transmitted within the same bandwidth. From November 2009, KBS has been preparing an advanced MMS service, 'Korea-View' which has both methods of encoding, MPEG-2 and H.264 that is compliant ATSC mobile standard, A/153. Korea-View is a kind of multi-channel broadcast service to provide one HD and 3 SD programs with the bandwidth of 6MHz. Terrestrial multi-channel service is required to focuse on expanding viewer service. Such Terrestrial multi-channel services will contribute to transferring to digital broadcasting and to extending the viewers' welfare. Due to advances in digital technology, Pay-TV channels has increased to hundreds. Even though digital switchover is being proceeded, terrestrial broadcasters have been unable to deliver multi-channel services. In this paper, technical features and differences of MMS and Koreaview will be analyzed regarding terrestrial multi-channel broadcasting services, and the politic direction will be proposed in accordance with introduction of future service.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.102-116
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• 2009

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level