• Journal of the Korea Society of Computer and Information
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• v.14 no.7
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• pp.65-72
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• 2009

This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

• Journal of the Korean Institute of Rural Architecture
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• v.16 no.1
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• pp.111-117
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• 2014

The aim of this study is to find out the pattern of Ger form, inner spatial composition of Mongolian Ger house, and to take a dig at the structural or symbolic elements of nomadic architecture of Ger. To the point of view of corresponding to living and space of housing, remarkable characteristics of Ger Architecture is able to pull down and recombine the structures of nomadic house. Even though urbanization of Mongolia has spreading rapidly in a whole nation, most of people preserves traditional housing pattern within Ger. The ways of survey are to study of traditional home of Mongolia, and then field work at residence or mountain area in Ulan Bator and Gorkhi Terelj National Park area. This survey contains the form, size, structure, spatial composition of living space, structure, and materials. There are three results as follows: First, the form of Ger house is like a pyramidal or crown roof style to approximate to the round shape of it. Usually they had lived in nomadic way of life, so the Ger had a movable and flexible structure. Second, the Ger is easy to build up and deconstruct to move or find a new pasture. Third, the Mongolian Ger structure is composed by mainly five elements that are Khana, Khaalga, Toono, Bagana, and Uni. It has a hierarchy of internal spaces which are classified to gender, orientation, and property.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.67-74
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• 2004

AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.165-168
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• 2000

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

• ETRI Journal
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• v.30 no.5
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• pp.707-717
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• 2008

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.121-127
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• 2012

An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.74-81
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• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Convergence Security Journal
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• v.16 no.7
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• pp.113-120
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• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.