• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 춘계학술대회
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• pp.548-549
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• 2015

무인 잠수정은 자율 무인잠수정(이하 'AUV' 또는 '자율무인잠수정'을 혼용)과 원격조정잠수정(이하 'ROV'로 지칭)으로 분류를 할 수 있다. ROV는 테더 게이블로 인한 작업 범위의 한계와 운동성능 효율이 떨어지는 단점을 지니고 있어, 테더 케이블이 필요 없는 AUV에 대한 필요성이 증대되고 있다. 추측 항법 시스템인 관성 항법 시스템(inertial navigation system, 이하 'INS'로 지칭)은 외부 도움없이 관성측정 장치(inertial measurement unit, 이하 'IMU'로 지칭)를 활용하여 구성된 시스템을 말한다. IMU는 자이로 스코프(gyroscope), 가속도계(accelerometer), 지자기(magnetic)센서로 구성된 측정 장치로 3개의 센서를 사용하여 상호 보정을 통한 기동 체의 위치, 속도 및 자세 정보를 제공한다. 복합항법시스템은 추측항법시스템이 가지는 누적오차와 측위 항법시스템이 가지는 외부환경에 대한 단점을 상호 보완하는 방법으로 연구가 진행 중이다. 하지만 심해서 또는 해양의 특성에 따라 측위 시스템이 사용되지 못하기 때문에 추측 항법시스템의 다양한 관성 센서를 활용한 상로 보완과 신호처리 방법을 통한 연구 개발이 진행 중이다. 다양한 센서 정보를 통합하는 목적으로 칼만 필터와 같은 최적 필터기법이 보편적으로 사용되고 있다. 칼만 필터는 확률 선형 시스템에 대하여 공정잡음 및 측정 잡음이 가우시안 확률 분포를 따를 때 최적의 추정자가 된다. 또한 가우시안 조건을 만족하지 않는 경우에도 선형 추정자 중에 추정 오차의 분산이 가장 작은 추정자이다. 칼만 필터가 최상의 성능을 발휘 하려면 공정잡음과 측정 잡음의 실제 값을 정확히 알아내는 것이 중요하다. 잡음 수준에 대한 정보가 부정확 할 경우 칼만 필터는 발산 할 수 있기 때문에 시스템에서 잡음 수준의 공산은 칼만 필터의 최적 이득을 결정하는 중요한 요소로 추정치에 큰 영향을 준다. 따라서 칼만 필터를 추측항법시스템에 적용 시킬 경우 실제 모텔의 잡음 공분산을 정확히 추정할 수 있는 기법이 요구된다. 추측항법시스템은 다양한 센서를 활용하기 때문에 움직이는 기동 표적에 적용시 잡음공분상이 변하기 때문에 항법시스템이 저하 될 수 있다. 본 연구에서는 다양한 센서를 융합하여 해양 생체 로봇의 정밀 자세 제어가 가능한 시스템을 제안하고자 한다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}