• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1004-1008
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• 2012

The effect of address discharge characteristics by selective reset method is investigated to prevent the weakness of address discharge in the middle of a TV-field without increase of the black luminance. To reduce black luminance in AC PDP usually, the first subfield during one TV frame adopted the conventional rising ramp-reset waveform, whereas the other subfields adopted the subsidiary reset waveform without rising ramp type. As the wall charge for the address discharge was accumulated by only the rising ramp waveform during the first reset period, the wall charge on three electrodes was disappeared as time passed and the address discharge would be weakened in the rear subfields. To prevent a reduction of the address discharge characteristics without decrease the black luminance, the modified rising ramp reset waveform was adopted only in the sixth subfield. As a result, a modified driving method could improve the address discharge characteristics compared with selective reset driving scheme with almost the same black luminance.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1544-1545
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• 2006

In this paper, we present a new reset waveform for a large-sustain-gap structure in at PDPs. In the driving of the large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address being a cathode, which causes lots of trouble in stabilizing a reset discharge. To solve these problems, we use the square pulse instead of the conventional rising ramp pulse. Before making a strong discharge between the address (cathode) and scan (anode) electrodes, we make a priming discharge between the address (anode) and the scan (cathode) electrodes to stabilize the strong discharge in which the address electrodes are the cathode. With this scheme, we obtained 60V minimum address voltage and 145V maximum address voltage in $250{\mu}m$ and $350{\mu}m$ gap structures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.125-131
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• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.