• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1635-1645
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• 1999

In this paper, an intelligent resynthesis technique for timing optimization at the architecture-level has been studied. The proposed technique can remedy the problem which may occur in combinational timing optimization techniques applied to circuits which have the hierarchical subblock structure at the architectural-level. The approach first tries to maintain the original hierarchical subblock while minimizing the longest delay of whole circuit. This paper tries to find a new approach to timing optimization for circuits which have hierarchical structure at architectural-level, and has verified its effectiveness experimentally. We claim its usefulness from the fact that most designers design the circuits hierarchically due to the increase of design complexity.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.593-605
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• 2014

In this paper, we propose the efficient HW/SW co-design method of light-weight cryptography such as HIGHT, PRESENT and PRINTcipher using GEZEL. At first the symmetric cryptographic algorithms were designed using the GEZEL language which is efficiently used for HW/SW co-design. And for the improvement of performance the HW optimization theory such as unfolding, retiming and so forth were adapted to the cryptographic HW module conducted by FSMD. Also, the operation modes of those algorithms were implemented using C language in 8051 microprocessor, it can be compatible to various platforms. For providing reliable communication between HW/SW and preventing the time delay the improved handshake protocol was chosen for enhancing the performance of the connection between HW/SW. The improved protocol can process the communication-core and cryptography-core on the HW in parallel so that the messages can be transmitted to SW after HW operation and received from SW during encryption operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.109-111
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• 2002

We have demonstrated all-opticalflip-flop based on optical bistability in a SOA/DFB-SOA with broadband gain. Input signal with the wavelength of 1340.23 nm or 1680.93 nm and the current of about 98% of the lasing threshold is injected into theDFB-SOA. Current injected into SOA is 80 mA All-optical flip-flop has various applications such as all-optical memory, demultiplexing, packet-header buffering, and retiming.

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.160-161
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• 2003

완전 광 3R(Retiming, Reshaping, Reamplification) 재생기는 WDM 시스템과 광 네트워크의 크기를 쉽게 확장시키기 위하여 필요한 매우 중요한 소자이다. 완전 광 3R 재생기의 구현에서 입력 광 신호로부터 광 클락을 추출하는 기술은 매우 중요한 기술이다. 이러한 광 클락 추출기술을 구현하기 위하여 모드락 레이저 다이오드와 다중 전극 OFB 레이저에서 self-pulsation 현상을 이용하는 방법이 많이 연구되고 있다. 모드락 레이저 다이오드를 이용한 방법은 모드 락킹 주파수가 레이저의 공진기의 길이에 의해서 결정되기 때문에 공진기의 길이를 정확하게 조절해야 한다는 단점을 가지고 있는 반면에 다중 전극 DFB 레이저의 경우 self-pulsation 주파수를 전기적으로 튜닝할 수 있다는 장점을 가지고 있다. (중략)

• Smart Media Journal
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• v.4 no.4
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• pp.120-129
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• 2015

Explosion effect on CG (Computer Graphic) a visual effect on which a higher degree of technological difficulty is required with a variety of effect elements such as Fire, Smoke, Flame, Dust, Debris, etc. integrated on it. As skills for CG software have been advanced, solutions loaded with functions of various fluid simulation have been developed. So more realistic special effects came to be available. However, in Korea, it depends just on CG program functions. Besides, enough R&D's concerned have not been followed up. Accordingly, this study is aimed at offering a production method that may effectively implement more realistic explosion effects under experimentations. To begin with, the study derives problems through a precedent study of the implementation of existing explosion effects. Then to solve them, experimental studies are performed depending on four solutions. There are accesses to the four solutions: first, Numerous Turbulent Flow, a method to allow an attribute of turbulent air in the stage of fluid simulation; second, Cache Retiming Solution produced in script; third, Multiple Volume Container based on cached data; and fourth, RGB Lighting Pipeline, a method to enhance the completion of the result from the stage of composition. Characteristics of effects applied in each stage and consecutive connections of them proved the effective implementation of more realistic explosion effects. This study may not only suppose the production method for efficient explosion effects differentiated from the previous ones but also be utilized as basic data for relevant researches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.485-493
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• 1990

Timing recovery for recently proposed nonlinear minimum-bandwidth systems is of concern since most conventional methods fail for these systems. As a method to surmount this retiming difficulty, this paper proposes the fourth-power-law method. The feasibility of the proposed method for minimum-bandwidth systems is shown through a rigorous analysis. Furthermore, extensive computer simulations are used to determine the best configurational strategy for various filters around the fourth-power nonlinear process. It is found that no intermediate filtering is necessary in general and even the pre-filtering can be omitted for systems having symmetric power spectral densities.

• ETRI Journal
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• v.35 no.4
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3181-3183
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• 1999

A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.63-73
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• 1999

This paper presents new pipeline architecure for low power and high speed digital FIR filters. The proposed architecture based on retiming technique achieves enhancement on speed by sharing the input delay stage with multiplication of input data and on power combined with supply voltage scaling down technique. An 8-tap digital FIR filter for PRML disk-drive read channels adopting the proposed pipeline architecture has been designed and fabricated with 0.8${\mu}m$ CMOS double metal process technology. Measured results show that the designed FIR filter operates to 192 MHz in average and dissipates 1.22 mW/MHz at 3.3.V power supply. As a result, the proposed architecture improves speed by about 16% and reduces power dissipation by about 23% when operating at the same throughput.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.