• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.180-182
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• 1993

A distance protection algorithm for detecting faults at power transmission lines is presented in this paper. The algorithm is based on the differential equation related to the voltage and the current at an equivalent circuit of a transmission line which is composed of the lumped resistance and inductance. The presented integration method has high performance at though the fault voltage and the current are heavily distorted with the DC offset and harmonics which occurred at transient states after faults.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.627-634
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the complimentary bifilar archimedean spiral resonator(CBASR) is presented for reducing the phase noise characteristic. A CBASR has compact dimension, a sharp skirt characteristic in stopband, a low insertion loss in passband, and a large coupling coefficient value, which makes a high Q value and improve the phase noise of VCO. The proposed VCO has the oscillation frequency of 2.396~2.502 GHz in the tuning voltage of 0~5 V, the output power of 7.5 dBm and phase noise of -119.16~-120.2 dBc/㎐ at the offset frequency of 100 kHz in tuning range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.69-75
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• 2010

In this paper, with using the clapp type VCO(Voltage Controlled Osillator) configuration a wideband frequency synthesizer in UHF band is proposed. In order to design a wideband frequency synthesizer, the variation of phase in the negative resistance circuit as well as the load circuit was analyzed. Based on this result we propose a method to widen the operation range of the VCO. A frequency synthesizer using the proposed wideband VCO was designed and fabricated. It is shown that the synthesizer has the operating frequency range of 740~1,530 MHz by 0~5 V varactor tuning voltage, and it had the output power of 2~-6 dBm. Moreover, the phase noise measured as -77 dBc/Hz at 10 kHz offset, and as -108 dBc/Hz at 100 kHz offset from the oscillation frequency.

• Phonetics and Speech Sciences
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• v.14 no.3
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• pp.11-25
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• 2022

From simultaneous recordings of the external photoglottography, intra-oral air pressure (P_io), airflow and acoustic data from four native Seoul Korean speakers (2 male and 2 female), we have found that the two fricatives are not significantly different in glottal opening peak and airflow peak height either word-initially or word-medially and that the duration of aspiration is significantly reduced in word-medial /s/, compared to those in word-initial /s/, not in /s'/. We have also found that the duration of a high P_io plateau is significantly longer in /s/ than in /s'/ both word-initially and word-medially and that airflow resistance (R=P_io/U) at the onset and offset of a P_io plateau and at the time of airflow peak height is significantly higher in /s'/ than in /s/ across the contexts. However, the differences in P_io peak and F0 are not significant. In addition, the transition time to reach airflow peak height from the offset of a P_io plateau is found to be significantly longer in /s/ than /s'/ in both word-initial and word-medial positions. No significant differences in glottal opening peak and airflow peak height confirm that /s/ is specified as [-spread glottis] like /s'/. As for the other significant differences, we propose that /s/ is [-tense], and /s'/ [+tense].

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.715-720
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• 2012

This study presents a hybrid balanced voltage controlled oscillator (VCO) circuit which is suitable for low phase noise operation at sub-1V supply voltages. Half circuits of the proposed VCO use the varactor-integrated feedback capacitors in their respective circuit. The varactor-integrated feedback capacitors further increase the negative resistance of the equivalent tank thereby ensuring stable start-up of oscillation even at the sub-1V supply voltage. In addition, this work theoretically analyses the phenomenon of the increase of the negative resistance. Simulation results using a $0.18{\mu}m$ RF CMOS technology exhibit the phase noises of -122.4 to -125.5.8 dBc/Hz at 1 MHz offset from oscillation frequency of 4.87 GHz over the supply voltages of 0.6 through 0.9 V.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.468-477
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• 2007

The DTC of voltage source inverter-fed PMSMs is based on hysteresis controllers of torque and flux. It has several advantages, namely, elimination of the mandatory rotor position sensor, less computation time, and rapid torque response. In addition, the stator resistance is the only parameter, which should be known, and no reference frame transformation is required. The DTC theory has achieved great success in the control of induction motors. However, for the control of PMSM drives proposed a few years ago, there are many basic theoretical problems that must be clarified. This paper describes an investigation into the effect of the zero voltage space vectors in the DTC system and points out that if using it rationally, not only can the DTC of the PMSM drive be driven successfully, but torque and flux ripples are reduced and overall performance of the system is improved. The implementation of DTC in PMSM drives is described and the switching tables specific for an interior PMSM are derived. The conventional eight voltage-vector switching table, which is namely used in the DTC of induction motors does not seem to regulate the torque and stator flux in a PMSM well when the motor operates at low speed. Modelling and simulation studies have both revealed that a six voltage-vector switching table is more appropriate for PMSM drives at low speed. In addition, the sources of difficulties, namely, the error in the detection of the initial rotor position, the variation of stator resistance, and the offsets in measurements are analysed and discussed.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1591-1597
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• 2003

In this paper, Active Resonator Oscillator using active inductor and active capacitor with HEMTs(agilent ATF­34143) is designed and fabricated. Active inductor with ­25$\Omega$ and 2.4nH in 5.5GHz frequency band and Active capacitor with ­14$\Omega$ and 0.35pF is designed. Active Resonator Oscillator for LO in ISM band(5.8GHz) is designed with active inductor and active capacitor. Active Resonator Oscillator has been simulated by Agilent ADS 2002C. Active Resonator oscillator implemented on the substrate which has the relative dielectric constant of 3.38, the height of 0.508mm, and metal thickness of 0.018mm. This Active Resonator Oscillator shows the oscillation frequency of 5.68GHz with the output power of ­3.6㏈m and phase noise of ­81㏈c/Hz at the offset frequency of 100KHz.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.118-125
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• 2003

This paper presents a 5.8-㎓ oscillator that uses a novel defected ground structure(DGS), which is etched on the metallic ground plane. As the suggested defected ground structure is the structure for mounting an active device, it is the roles of a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM simulation ,md simple circuit analysis method. In order to demonstrate a new DGS oscillator, we designed the oscillator at 5.8-㎓. The experimental results show 4.17 ㏈m output power with over 22 % dc-to-RF power efficiency and - 85.8 ㏈c/Hz phase noise at 100 KHz offset from the fundamental carrier at 5.81 ㎓.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.