• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1086-1096
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• 2004

In case of a multimedia application which deals with streaming data, in terms of cache management, cache loses its efficiency due to weak temporal locality of the data. This means that when data have been brought into cache, much of the data are supposed to be replaced without being accessed again during its service. However, there is a good chance that such multimedia data has a commanding locality in it. In this paper, to take advantage of the memory reference regularity which typically innates even in the multimedia data showing up its weak temporal locality, a method is suggested. The suggested method with the feature of dynamic regular-stride reference prefetching can identify for 2-dimensional array format(block pattern). The suggested method is named as block-reference-prediction-technique (BRPT) since it identifies a block pattern and place an address to be prefetched by the regulation of the block format. BRPT proved to be reassuring to reduce memory reference time significantly for applications having abundant block patterns although new rule has complicated the prefetching system even further.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.11-20
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• 2004

Multimedia data processing in streaming pattern contains high spatial locality and low temporal locality. This paper has proposed a dynamic data prefetching scheme that fully exploits the regularity between memory addresses referred consecutively. Compared to the existing data Prefetching scheme, the Proposed scheme can reduce data Prefetching error when an application divides an way into smaller blocks and processes them block by block. Experimental results on various media benchmark programs show the proposed scheme predicts memory addresses more accurately and results in better performance than existing prefetching schemes.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.